Mitsubishi DS5000TK, DS907x SIP manual RPC Protocol, DMA Operation, Dbbout, 103

USER'S GUIDE

RPC PROTOCOL

Data is written to the microprocessor by the host CPU and is placed in the DBBIN. At this time, the IBF flag is set in the RPC Status Register. If enabled by the IBI bit in the RPCTL register, an IBI interrupt will occur. No fur- ther updates of the DBBIN will be allowed until the buffer is read by the microprocessor. Once read, the IBF flag will be cleared. When the DBBOUT is written to by the microprocessor, the OBF is set in the RPC Status Reg- ister (STATUS). No future writes are allowed until the DBBOUT is read by the external host. The OBF is cleared when such a read takes place.

The RPC mode provides a simple interface to a host processor. In general, four control bits specify the operation to be performed. This works as shown in Fig- ure 12±3.

These conditions provide the basis of a complete slave interface. The protocol for such communications might operate as follows:

1.Host processor reads STATUS.

2.If DBBIN is empty (IBF=0), host writes a data or com- mand word to DBBIN.

3.If DBBOUT is full (OBF=1), host reads a word from

DBBOUT.

4.RPC detects IBF flag via interrupt or polling. Input data or command word is processed.

5.RPC recognizes OBF=0, and writes a new word to

DBBOUT.

Timing diagrams in RPC AC electrical specifications illustrate the operation of the RPC mode bus transfers. A DBBOUT read places the contents of DBBOUT on the data bus and clears OBF. A STATUS register read places the contents of the STATUS register on the data bus. A write to DBBIN causes the contents of the data bus to be transferred to the DBBIN, and the IBF flag (STATUS) is set. A command write operates in the same way. The DS5001FP or DS5002FP can deter- mine whether the write was data or command by examining the IA0 bit in the STATUS register. This bit will be equal to the A0 input of the most recent valid host write operation.

DMA OPERATION

If DMA transfers are required, the RPC mode can sup- port them. DMA transfers are initiated by setting the DMA bit in the RPCTL register. The DRQ output is de± asserted at this time. DRQ can be asserted by writing a 1 to the DRQ line (P2.6) from software. The host CPU must respond by pulling the DACK input low. Data can then be transferred according to the user's required pro- tocol. DMA mode can be cancelled by clearing the DMA bit, by a reset, or by clearing the RPCON bit of the RPCTL control register to leave the RPC mode.

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