Mitsubishi DS907x SIP Interrupt Enable Register, LabelIE Register Address 0A8H, SCON.0, ET1, EX1

USER'S GUIDE

Initialization:	Cleared to a 0 on any type of reset.
SCON.0:	RI
ªReceive Interruptº:	Status bit used to signal that a serial data word has been received and
	loaded into the receive buffer register. In mode 0, it is set at the end of the 8th
	bit time. It is set at the mid±bit time of the incoming stop bit in all other modes
	of a valid received word according to the state of SM2.

INTERRUPT ENABLE REGISTER
Label:IE					Register Address: 0A8H
D7	D6	D5	D4	D3	D2	D1	D0
EA	±	±	ES	ET1	EX1	ET0	EX0
Bit Description:
IE.7:		EA
ªEnable All Interruptsº:		When set to 1, each interrupt except for PFW may be individually enabled or
		disabled by setting or clearing the associated IE.x bit. When cleared to 0,
		interrupts are globally disabled and no pending interrupt request will be ac-
		knowledged except for PFW.
IE.4:		ES
ªEnable Serial Interruptº:		When set to 1, an interrupt request from either the serial port's TI or RI flags
		can be acknowledged. Serial I/O interrupts are disabled when cleared to 0.
IE.3:		ET1
ªEnable Timer 1 Interruptº:		When set to 1, an interrupt request from Timer 1's TF1 flag can be acknowl-
		edged. Interrupts are disabled from this source when cleared to 0.
IE.2:		EX1

ªEnable External Interrupt 1º: When set to 1, an interrupt request from the IE1 flag can be acknowledged. Interrupts are disabled from this source when cleared to 0.

IE.1:ET0

ªEnable Timer 0 Interruptº: When set to 1, an interrupt request from Timer 0's TF0 flag can be acknowl- edged. Interrupts are disabled from this source when cleared to 0.

IE.0:EX0

ªEnable External Interrupt 0º: When set to 1, an interrupt from the IE0 flag can be acknowledged. Inter- rupts are disabled from this source when cleared to 0.

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