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Mitsubishi DS907x SIP manual Tcon Register CONTROL/STATUS Bits ±2, TMOD.5, TMOD.4, TMOD.1, TMOD.0

Models: DS5000TK DS907x SIP

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USER'S GUIDE

TMOD.5, TMOD.4:	Timer 1 Mode Control
ªMode Selectº	These bit select the operating mode of the associated timer/counter as fol-
	lows:
	M1	M0
	0	0	Mode 0: Eight bits with 5±bit prescale
	0	1	Mode 1: 16 bits with no prescale
	1	0	Mode 2: Eight bits with auto±reload
	1	1	Mode 3: Timer 1 ± Stopped
Initialization:	Cleared to 0 on any reset.

TMOD.1, TMOD.0:	Timer 0 Mode Control
ªMode Selectº	These bit select the operating mode of the associated timer/counter as fol-
	lows:
	M1	M0
	0	0	Mode 0: Eight bits with 5±bit prescale
	0	1	Mode 1: 16 bits with no prescale
	1	0	Mode 2: Eight bits with auto±reload
	1	1	Mode 3: Timer 0 ± Two 8±bit timers
Initialization:	Cleared to 0 on any reset.

TCON REGISTER CONTROL/STATUS BITS Figure 13±2

Bit Description:

TCON.7:	TF1
ªTimer 1 Overflow Flagº:	Status bit set to 1 when Timer 1 overflows from a previous count value of all
	1's. Cleared to 0 when CPU vectors to Timer 1 Interrupt service routine.
Initialization:	Cleared to 0 on any type of reset.

TCON.6:	TR1
ªTimer 1 Run Controlº:	When set to a 1 by software, Timer 1 operation will be enabled. Timer 1 is
	disabled when cleared to 0.
Initialization:	Cleared to 0 on any type of reset.

TCON.5:	TF0
ªTimer 0 Overflowº:	Status bit set to 1 when Timer 0 overflows from a previous count value of all
	1's. Cleared to 0 when CPU vectors to Timer 0 interrupt service routine.
Initialization:	Cleared to 0 on ay type of reset.

TCON.4:	TR0
ªTimer 0 Run Controlº:	When set to a 1 by a software, Timer 0 operation is enabled. Timer 0 is dis-
	abled when cleared to 0.
Initialization:	Cleared to 0 on any type of reset.

050396 105/173

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Image 106

Mitsubishi DS907x SIP, DS5000TK manual Tcon Register CONTROL/STATUS Bits ±2, TMOD.5, TMOD.4, TMOD.1, TMOD.0

Contents

Table of Contents Software Security IntroductionSeparate ADDRESS/DATA BUS High Reliability Operation Large Nonvolatile MemoryIN±SYSTEM Loading Module Description ON±BOARD Memory PackageDS5000T Soft Microcontroller Module Product DescriptionDS5000FP Soft Microprocessor Chip DS2250T Soft Microcontroller ModuleDS5002FP Secure Microprocessor Chip DS2251T 128K Soft Microcontroller ModuleDS2252T Secure Microcontroller Module Module Description Selection GuideChip Description Maximum Speed Part Number Speed Clock Part NumberSecure Microcontroller Architecture Secure Microcontroller Architectural Block Diagram Figure Program/Data RAM Interface Timed Access LogicParallel I/O High±Reliability CircuitryWatchdog Timer Resident Loader ROMSecure Microcontroller Memory MAP ±1 Programmers GuideSecure Microcontroller Memory Organization Internal RegistersScratchpad Register MAP ±2 PSW.4±3 R1±R0 Register Bank Select Program and Data MemoryBank Starting Address R0 DS5000 Series Memory Organization Important Application NoteMemory map. The first is the EA pin. The second is DS5000 Series Memory MAP ±3Overrides the condition of the EA pin as well DS5000 Series Mcon Register ±4 Bit Description DS5000 Memory Map ControlPA3 RA32/8 DS5001/DS5002 Memory OrganizationMCON.3 MCON.2 ECE2RG1 RG0 Range CE1 Access CE2 Access PA3 PA2 PA1 PA0 Partition BYTE±WIDE BUS Memory MAPCE1 CE3 CE4 Msel RG1 RG0 Program Data Program Access Data AccessPartitionable Memory MAP for DS5001/DS5002 Series ±5 CE1 CE2 CE3NON±PARTITIONABLE Memory MAP for DS5001, DS5002 Series ±6 DS5001/DS5002 Memory Mapped PeripheralsPeripheral Enables in the Data Memory MAP ±7 DS5001/DS5002 Memory Map ControlMCON.3 RG1 DS5001/DS5002 Series Mcon Register ±8PA3 PA2 PA1 PA0 RG1 PES MCON.2 PESRPCTL.4 Loading and Reloading Program MemoryRPCTL.5 Exbs RPCTL.0 RG0050396 23/173 Reloading Portions of a DS5000 Series Device ±10 Soft Reload of a DS5001/DS5002 Reloading a DS5001/DS5002 Series Device ±11 Special Function Registers DS5000 Series Special Function Register MAP ±12 ECE2DS5001/DS5002 Series Special Function Register MAP ±13 CRCPower Control Register Label Pcon Register Address 087HPCON.1 Stop PCON.3EPFWPCON.2 EWT PCON.0 IDLTimer Control Register Label Tcon Register Address 088HTCON.0 IT0 Timer Mode RegisterLabel Tmod Register Address 089H GateSerial Control Register LabelSCON Register Address 098HSCON.0 Interrupt Enable RegisterLabelIE Register Address 0A8H ET1Interrupt Priority Register LabelIP Register Address 0B8HRNGE3±0 DS5001 CRC RegisterLabel CRC Register Address 0C1H CRC.1 MDMPA3 PA2 PA1 PA0 DS5000 Memory Control RegisterLabelMCON Register Address 0C6H RA32/8Label Mcon Register Address 0C6H DS5001 Mcon RegisterMCON.0 Accessed by Movx instructions on the Byte±wide bus Program Status Word Register LabelPSW Register Address 0D0HRPCTL.7 RNR DS5001/DS5002 RPC Control RegisterLabel Rpctl Register Address 0D8H RPCTL.3 IBIRPCTL.1 Rpcon DS5001/DS5002 RPC Status RegisterLabel RPS Register Address 0DAH IA0RPS.0 RPS.1IBF OBFADD A, R4 Instruction SETAddressing Modes Setb 00HAcall 100H Call to the subroutine at ±20 Branch to the location PC+2 ±Addressing AddressProgram Status Flags Instructions That Affect Flag SettingsFlags Instruction OV AC Data Reten Part Tion Current RAM Size Vendor Memory InterconnectRecommended SRAMs for USE with Soft Microcontrollers ±1 25C 40C 70CDS5000 Series Module Block Diagram ±2 Memory Interconnect of the DS5000FP ±1Óóóóóóóóó Ó Memory Interconnect of the Partitionable DS5001/DS5002 ±3Óóóóóóóó 52 14Ó GND Memory Interconnect Using the 128K Sram ±5 DS2251T±128 Block Diagram ±6 DS2252T±32 Block Diagram ±7 ÔôôôôôBattery Backed Circuits LITHIUM/BATTERY BackupData Retention Battery Lifetime Power Supply Slew Rate ±1Battery Attach Procedure Battery attached180 * 10±3 54 * 10±32400 + 75 * 10±9 * 24 21.68 * 10±3 Lithium Battery Usage Freshness SealCONTROL/STATUS Bits for Power Control ±1 Bit Description Power ManagementIdle Mode ªPower On ResetºPIN States in IDLE/STOP Modes ±1 Stop ModeMode Program ALE Psen Memory PCON.3 EpfwSecure Microcontroller Power Cycling Timing ±2 Voltage Monitoring CircuitryPartial Power Failures Power Fail InterruptTotal Power Failure Vpfw threshold is above the specified minimumSecure Microcontroller Power Management ±3 Reset VectorTimed Access ±1 Timed AccessSoftware Control Timed Access Protected Control Bits ±1 BIT Name Micro Version Location Description050396 66/173 0C7H, #055H 2nd TA Value Watchdog Timer ±2IP.7 Watchdog Timer Control Bits CRC Memory VerificationCRC.1 DS5001 CRC Register Address 0C1hRange 3±0 CRC.0CRC Code Example ±3 This routine tests the CRC±16 circuit in the DS5001FPSecurity Overview FeatureFirmware Security DS5001 DS5000 DS5002RAM Memory Security LockEncrypted Memory DS5000 Software Encryption Block Diagram ±1 DS5002 Software Encryption Block Diagram ±2050396 74/173 Encryption Key Encryption AlgorithmEncryption Key Selection and Loading Dummy Bus Access Dummy BUS Access Timing ±3Microprobe/Die Top Coating On±chip Vector RAMSelf±Destruct Input Random Number GeneratorDS5000FP / DS5000T / DS2250T Security Summary by PartDS5001FP / DS2251T Application Advanced Security Techniques External Circuits Change CodeTamper Protection Reset Sources Reset ConditionsReset Status Bits ±1 Reset Condition Reset Type Special Function Register Reset States ±1Register Power on Reset Timing ±2 Power On ResetChanical and some time is required to get the mass External Reset No±VLI Power On ResetWatchdog Timer Reset Memory Interrupts TIMERS/SERIAL Protection Application Reset Routine ExampleMemory Map Interrupts Timed ± DS5000 onlyMicroprocessor disables timer activity excluding TimersTively. Shown here is an example of Timer and Serial ProtectionInterrupt Sources Interrupt Source Enable BIT LocationInterrupts Interrupt Source Vector Address Flag Flag LocationMachine cycle when the interrupts are enabled. INT0 is Timer InterruptsPower±fail Warning Interrupt External InterruptsSimulated Interrupts Interrupt Request Sources ±1ET0 Interrupt Enable Control Bits ±2 Bit DescriptionEX0 Priority Flag Interrupt Source Interrupt PrioritiesInterrupt Priority Control Bits ±3 Bit Description IP.4Interrupt Acknowledge Sequence ±4 Interrupt AcknowledgeFlag Vector Address Interrupt Source 050396 94/173 PIN Name Parallel I/O OverviewPort 0 Functional Circuitry ±1 FunctionPort 1 Functional Circuitry Port 2 Functional CircuitryPort 3 Functional Circuitry Output FunctionsParallel Port Output Buffers Ports 1, 2, and 3 ±2 Input FunctionMnemonic Description READ±MODIFY±WRITE InstructionsReprogrammable Peripheral Controller RPC Port 0 D0±7Command USE of the RPC Mode ±3USE of the RPC Mode ±4 RPC InterruptsRPC Status Register ± Status Address 0DAH ±5 ST7 ST6 ST5 ST4 IAO IBF OBFDbbout RPC ProtocolDMA Operation 103RNR Exbs IBI DMA Rpcon RG0 Port 2 becomes the control signals as shown in ±3RPC Control Register ± Rpctl Address 0D8H ±6 Rpcon bit is setTMOD.6 Timer TMOD.2 Timer Programmable Timers Functional DescriptionTmod Register Control BIT Summary ±1 Bit Description TMOD.5, TMOD.4 Tcon Register CONTROL/STATUS Bits ±2TMOD.1, TMOD.0 Scribed for TR0, TF0, and INT0 TIMER/COUNTER Mode 0 and 1 Operation ±3Mode 107TIMER/COUNTER Mode 2 Operation ±4 108Timer 0 Mode 3 Operation ±5 109Serial Port Operating Modes ±1 Mode SYNC/ASYNC Baud ClockSerial I/O Function Description START/STOPSerial Port Control Register ±1 Bit Description Mode Function Word Length PeriodMode Sync Bits CLK Async Timer 1 Overflow ªXmit Bit 8ºSCON.0 SCON.2 RB8SCON.1 Baud Rate GenerationSmod Timer TH1 Timer 1 Baud Rate Generation ±2Synchronous Operation Mode Baud Rate BPS114 Mode 0 Block Diagram and Timing ±2 115Asynchronous Operation 116Smod BRG Clock Mode 2117 Serial Port Mode 1 Block Diagram ±3 118MODE2 and 3 Block Diagram ±4 119Application Serial Port Initialization Mode Function Word Length Baud ClockSerial I/O Operating Modes ET1 EX1 ET0 EX0 SM0 SM1 SM2 RENTB8 RB8 PT1 PX1 PT0 PX0TF1 TR1 TF0 TR0 Smod POR PFW WTR Epfw EWT Stop IDLIE1 IT1 IE0 123 Clock Source Input ±2 CPU Timing OscillatorCrystal Connection ±1 XTAL1Instruction Timing 125Expanded Program Memory Timing BYTE±WIDE RAM Instruction Execution Timing ±3126 Expanded Program Memory Fetch ±4 127Expanded Data Memory Write ±6 Expanded Data Memory Read ±5128 Complete RD cycle, including activation of ALE and RD Expanded Data Memory Timing129 DS5000FP DS5001/2FP Invoking the Bootstrap LoaderProgram Loading Introduction 130Exiting the Loader DS5000 SeriesDS5001/DS5002 Series 131132 MODEM=1 PROG=0Serial Load Configuration ±2 Serial Program Load Mode133 Crystal Freq MHz 300 1200 2400 AUTO±BAUD Rate DetectionBaud Rate 57600Command Line Syntax Bootstrap Loader InitializationCommand Line Interface Command Function Version→ 000AH AB → 00ABH Command SummariesBegin±address end±address ABC → 0ABCH Abcd → 0ABCDH Abcde → 0BCDEHByte Byte begin±address end±addressByte±1 byte±2 byte±3 byte±4 byte±5 P0 value P1 value P2 value P3 valueMcon Xon/XoffCRC/MCON/MSL/RPCTL byte MSLEillcmd Error Messages EargreqEextarg EilloptIntel HEX File Format 140Parallel Program Load Cycles ±4 Parallel Program Load Configuration ±3Parallel Program Load Operation 1418751±COMPATIBLE Program Load Cycles ±3 Parallel Program Load ModeMode RST Psen Prog P2.7 P2.6 P2.5Pulses specified, each with a low time of 90 to RPC Program Mode OperationParallel Programming Concerns 143DS1215 Phantom Time Chip DS5000T/DS2250T Functional Block Diagram ±1REAL±TIME Clock 144145 Pattern Comparison Register Description ±2 146DS1215 Register Entry Flowchart ±3 147Special Bits DS1215 Time Registers Description ±4Registers 148Time Register Examples ±5 149DS1283 Watchdog Timekeeper Chip 150Memory MAP DS2251T/DS2252T RTC Block Diagram ±6151 DS1283 REAL±TIME Clock Memory MAP ±7 152DS1283 REAL±TIME Clock Command Register ±8 DS1283 RTC Interrupts Alarm Maskbit Operation ±9Alarm Condition MaskApplication Using the DS5000T RTC DS1215 Example 155Wbyte 156RET 157158 Application Using the DS2251T RTC DS1283 Example 159160 161 162 163 RAM Loses Data When Powered Down TroubleshootingUnexplained Device Resets Time Microcontroller Reads the Wrong TimeSerial Port does not Work Unable to Invoke Stop ModeProgram will not Execute INT0 is Stuck LOW on DS2252T High Current Drain in Stop ModeData is Lost or Corrupted DS5000TK KIT does not Respond to KIT5K SoftwareDOS Instruction SET Details Mnemonic Instruction Code HEX Byte Cycle ExplanationDA a CLR a CPL aRR a RL aRLC a RRC aMnemonic Instruction Code HEX Byte CPL bit Bit = bit CLR bit Bit =Setb bit Bit = ANL C, bit = C and bitReti RETDptr NOP