Mitsubishi DS5000TK manual Parallel I/O, Program/Data RAM Interface, High±Reliability Circuitry

USER'S GUIDE

Parallel I/O

Four SFR's provide access for the four parallel I/O port latches. These I/O ports are denoted as P0, P1, P2, and P3. A total of 32 bits of parallel I/O is available through these I/O ports. However, up to 16 bits are sacrificed when the Expanded Bus mode is used to interface to ex- ternal memory and up to six bits may be sacrificed if any external interrupt inputs, timer counter inputs, or serial I/O functions are used. When using the Byte±wide bus, ports are not affected.

Program/Data RAM Interface

Secure Microcontrollers provide a non±multiplexed Byte±wide bus that connects to external SRAM. They also make this RAM nonvolatile, decode memory ac- cess for it, and write±protect portions designated as pro- gram memory. The Byte±wide bus consists of up to 16 address lines (depending on the version), eight data lines, read/write control, and decoded chip enables. When accessing the SRAM via its Byte±wide bus, there is no activity on the ports. Thus if memory access is re- stricted to this bus, all ports are free for use by the application. In module form, the microprocessor is al- ready connected to SRAM via the Byte±wide bus mak- ing program and data memory access appear internal.

Secure Microprocessors can also access memory us- ing the multiplexed Expanded Bus consisting of Port 0 and 2, WR (P3.6) and RD (P3.7). This is usually undesir- able since it consumes port pins that can be used for other activity. If Expanded bus access is desired, up to 64K ROM and 64K RAM can be accessed in the same manner as a traditional 8051. Each version has different provisions for using the Expanded bus, depending on memory map and user's configuration. These issues are discussed under the Programmer's Guide.

High±Reliability Circuitry

This feature ensures proper operation of the micro and maintains the contents of the Program/Data RAM in the absence of VCC using a self±contained lithium energy source. The logic provided includes the Power Fail Warning Interrupt, Automatic Power Down and Power On Reset. As a result, the Program/Data RAM may be modified whenever necessary during execution of the user's software but will remain unchanged when VCC is absent. The circuitry also maintains the Internal

Scratchpad RAM and certain Special Function registers during a power down condition.

Software Encryption Logic

DS5000 and DS5002 series parts provide software se- curity circuits that include the Address Encryptor, Data Encryptor, and the Encryption Key Word. When the de- vice is operating in the Encryption mode and using the Program/Data RAM, the Address Encryptor is used to transform ªlogicalº addresses on the Internal Address Bus into encrypted addresses which appear on the Byte±wide Memory Bus to the RAM. Similarly, the Data Encryptor transforms data on the Internal Data bus into encrypted data during write operations on the Byte± wide Memory bus. When data is read back, the Data En- cryptor restores it to its true value. Although each en- cryptor uses its own algorithm for encrypting data, both depend on the Encryption Key Word stored on±chip.

Security Lock Logic

The Security Lock logic prevents a read or write to any Program/Data RAM location using the bootstrap loader. In addition, it inhibits the device from fetching code in the Expanded Bus Mode. By disabling access to key inter- nal resources, this feature precludes unauthorized dis- assembly of application software contained in Program/ Data RAM. In contrast with an EPROM security bit, clearing the Security Lock wipes the entire RAM area.

Vector RAM

The Vector RAM is used to contain the reset and inter- rupt vector code when the Soft Microcontroller is operat- ing in the Encryption mode. This feature is included to insure the security of the application software. The op- eration of the Vector RAM as well as the reason for its inclusion in the architecture are discussed in the Software Security section.

Timed Access Logic

The Timed Access logic is used to protect against inad- vertent changes to configuration and to the Program RAM in the event of a loss of software control. The pro- tected configuration parameters include the Partition Address bits in the MCON register, as well as the Enable Watchdog Timer bit, Stop Mode bit, and Power On Re- set bit in the PCON register.

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