Mitsubishi DS5000TK, DS907x SIP manual Secure Microcontroller Architecture

USER'S GUIDE

SECTION 3: SECURE MICROCONTROLLER ARCHITECTURE

Introduction

The Secure Microcontroller family is based on an 8051 compatible core with a memory interface and I/O logic build around it. Many functions are identical to standard 8051s and are documented here for completeness. In general, most architecture features apply to all mem- bers of the Secure Microcontroller family. When there is a difference between versions, this will be mentioned. A block diagram of the microcontroller core is shown in Figure 3±1 below.

Bus Organization

There are four major busses in the Secure Microproces- sor: the Internal Data Bus, the Internal Address Bus, the Byte±wide Memory Bus, and the Expanded Bus. All ad- dresses and data which are transferred during program execution are passed on the Internal Address and Data Busses. User Program and Data Memory is always ac- cessed from either the byte±wide Program/Data RAM or from external memory located on the Expanded Bus.

The Byte±wide Memory Bus is used for access to Pro- gram/Data RAM in the same fashion as an 8051 Family device would access internal ROM or EPROM memory. This bus can be used in place of the Expanded Bus, freeing Port 2 and Port 0 pins for general I/O use.

CPU Registers

All of the CPU registers are mapped as Special Function Registers (SFR's) and are identical in number and func- tion to those present within the 8051. These registers are described briefly below:

Accumulator

The Accumulator (A) is used as either a source or des- tination register in all arithmetic instructions. It may also be used in most other types of instructions.

Stack Pointer

The Stack Pointer (SP) is an 8±bit register which is used to mark the location of the last byte of data stored in the stack. The stack itself may be located anywhere in the on±chip 128±byte Scratchpad register area. The Stack Pointer pre-increments during a stack push and post- decrements during a stack pop.

B Register

The major function of the B register is as a source and destination register during multiply and divide instruc- tions. It may also be used as a scratchpad register.

Program Status Word

The Program Status Word (PSW) contains status flags that are set according to the results of a previously executed instruction. In addition, the PSW contains reg- ister bank select bits.

Data Pointer

The Data Pointer (DPTR) is used to access Data Memory that may be mapped into Byte±wide Data RAM or onto external memory devices on the Expanded Bus. It is accessed by the user's program as either two 8±bit Special Function registers or as a 16±bit register with certain instructions.

Scratchpad Registers

Scratchpad registers are 128 registers where data may be stored directly. They are addressed from 00H to 7FH and may be accessed by a MOV instruction. Included in the scratchpad area are four 8±byte banks of working registers. These registers are not part of the data memory map.

Serial I/O

The on±chip serial I/O port is comprised of a receive data buffer, a transmit data buffer, and a control register. Both the receive data buffer and the transmit data buffer are accessed in a single location (SBUF) in the Special Function Register map. The control register (SCON) is accessed in an separate location. When the serial I/O function is enabled, two external I/O pins (P3.0, P3.1) are re±assigned in hardware to serve the transmit and receive data functions.

Programmable Timers

Two 16±bit programmable timers are included that can perform various timing and counting functions. A total of four registers (TH1, TL1, TH0, and TL0) access the up- per and lower halves of each of the two timer/counters. A single control register (TCON) is used to select the various operating modes of the two timers. Two external I/O pins (P3.4, P3.5) may be programmed to serve as external counter inputs, one pin for each of the two tim- er/counters.

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