Mitsubishi DS907x SIP Interrupt Acknowledge Sequence ±4, Flag Vector Address Interrupt Source

USER'S GUIDE

INTERRUPT ACKNOWLEDGE

The various interrupt flags are sampled an latched once every machine cycle, specifically during clock phase S5P2 (see CPU timing section) regardless of other in- terrupt related activity. Likewise, the latched states of the flags are polled once every machine cycle for the sampling which took place during the previous machine cycle.

A complete interrupt acknowledge sequence consists of a total of four machine cycles, labeled as IA1, IA2, IA3, and IA4 in Figure 11±4. The various interrupt flags are sampled and latched once every machine cycle, specifically during clock phase S5P2. This is shown in the diagram as IA1. If one or more pending interrupt reg- isters are latched, then during the following machine cycle (IA2) priority is resolved between one or more ac- tive interrupt requests.

Also during IA2, the hardware checks the state of the machine to insure that the following criteria are met be- fore servicing the pending interrupt:

a)The current cycle is not part of an instruction within an interrupt service routine of an interrupt of equal or higher priority.

b)The current cycle is not the final machine cycle of an instruction which accesses the IP or IE registers.

If the above criteria are met during IA2, then a long call will be executed during IA3 and IA4 to the vector loca- tion of the pending interrupt source of highest priority and the interrupt acknowledge sequence will be com- plete. The vector locations for the various sources are summarized below.

FLAG	VECTOR ADDRESS	INTERRUPT SOURCE
PFW	002BH	Power Fail Warning
IE0	0003H	External Interrupt 0
TF0	000BH	Timer Interrupt 0
IE1	0013H	External Interrupt 1
TF1	001BH	Timer Interrupt 1
RI+TI	0023H	Serial I/O Interrupt

If the criteria during IA2 are not met, then the interrupt acknowledge sequence is aborted and the interrupt re-

quest latches will again be polled on the following ma- chine cycle (which would have been IA3).

INTERRUPT ACKNOWLEDGE SEQUENCE Figure 11±4

IA1	IA2	IA3	IA4
INTERRUPT	POLLING		LONG CALL TO	INTERRUPT
	CYCLE		VECTOR ADDRESS	SERVICE
LATCHED
				ROUTINE
(S5P2)

INTERRUPT

GOES

ACTIVE

The first criteria for the continuation of an interrupt ac- knowledge cycle is designed to maintain the priority relationship between interrupts and their priority level assignment. As a result, pending interrupt sources can- not be acknowledged during the execution of service routines of interrupts which are of equal or higher prior- ity. Interrupt acknowledges are not allowed during an RETI instruction or during instructions which access IP

or IE in order to insure that at least one more instruction will be executed before an interrupt is serviced.

The interrupt request flags are sampled and latched during every machine cycle regardless of the other in- terrupt activity on the device. Each time an attempt ac- knowledge takes place during IA2, it is based on the latched value of the flags during the previous machine

050396 93/173

94