114 | Mitsubishi DS907x SIP, DS5000TK guide

USER'S GUIDE

was originally written into bit position D8. During the final shift register operation, another 0 is shifted in from the left so that the Transmit Shift register contains all 0's. Also at this time, the Transmit Interrupt flag (TI) is set and a serial interrupt will be generated if enabled.

During serial data transmission in Mode 0, SHCLK is ini- tially driven low onto the TXD pin at S3 of the machine cycle when D0 is output. During the time that the data word is shifted out, SHCLK will be low during S3, S4, and S5 and high during S6, S1, and S2 of every machine cycle.

A serial data word will be shifted into the Receive Shift register as soon as the condition REN=1 and RI=0 is sa- tisfied. This condition can only be initiated by a write to the SCON register from the application software. At S6P2 of the second machine cycle following the write to SCON, the RXD pin will be sampled and the value (D0)

will be shifted into the MSB position of the Receive Shift register. Seven more shifts will occur at S6P2 of subse- quent machine cycles until the entire 8±bit word has been shifted into the Receive Shift register.

The SHCLK signal will be initially output low on the TXD pin starting at S3P1 of the same machine cycle in which D0 was sampled. As in the case described above for transmit, SHCLK will be low during S3, S4, and S5 and high during S6, S1, and S2 of every machine cycle.

After the last data bit (D7) has been shifted in, the control logic will immediately load the Receive Data Buffer at the SBUF register address with the contents of the Re- ceive Shift register. At S1P1 of the 10th machine cycle following the write to SCON which initiated reception, the Receive Interrupt flag will be set and a serial inter- rupt will be generated if it has been enabled.

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Mitsubishi DS907x SIP, DS5000TK manual 114

Contents

Table of Contents Introduction Software SecuritySeparate ADDRESS/DATA BUS High Reliability Operation Large Nonvolatile MemoryIN±SYSTEM Loading Module Description ON±BOARD Memory Package DS5000T Soft Microcontroller Module Product DescriptionDS5000FP Soft Microprocessor Chip DS2250T Soft Microcontroller Module DS2251T 128K Soft Microcontroller Module DS5002FP Secure Microprocessor ChipDS2252T Secure Microcontroller Module Module Description Selection GuideChip Description Maximum Speed Part Number Speed Clock Part Number Secure Microcontroller Architecture Secure Microcontroller Architectural Block Diagram Figure Program/Data RAM Interface Timed Access LogicParallel I/O High±Reliability Circuitry Watchdog Timer Resident Loader ROM Secure Microcontroller Memory MAP ±1 Programmers GuideSecure Microcontroller Memory Organization Internal Registers Scratchpad Register MAP ±2 Program and Data Memory PSW.4±3 R1±R0 Register Bank SelectBank Starting Address R0 DS5000 Series Memory Organization Important Application Note DS5000 Series Memory MAP ±3 Memory map. The first is the EA pin. The second isOverrides the condition of the EA pin as well DS5000 Memory Map Control DS5000 Series Mcon Register ±4 Bit DescriptionPA3 RA32/8 DS5001/DS5002 Memory OrganizationMCON.3 MCON.2 ECE2 RG1 RG0 Range CE1 Access CE2 Access PA3 PA2 PA1 PA0 Partition BYTE±WIDE BUS Memory MAP CE1 CE3 CE4 Msel RG1 RG0 Program Data Program Access Data AccessPartitionable Memory MAP for DS5001/DS5002 Series ±5 CE1 CE2 CE3 NON±PARTITIONABLE Memory MAP for DS5001, DS5002 Series ±6 DS5001/DS5002 Memory Mapped Peripherals Peripheral Enables in the Data Memory MAP ±7 DS5001/DS5002 Memory Map Control MCON.3 RG1 DS5001/DS5002 Series Mcon Register ±8PA3 PA2 PA1 PA0 RG1 PES MCON.2 PES RPCTL.4 Loading and Reloading Program MemoryRPCTL.5 Exbs RPCTL.0 RG0 050396 23/173 Reloading Portions of a DS5000 Series Device ±10 Soft Reload of a DS5001/DS5002 Reloading a DS5001/DS5002 Series Device ±11 Special Function Registers DS5000 Series Special Function Register MAP ±12 ECE2 DS5001/DS5002 Series Special Function Register MAP ±13 CRC Power Control Register Label Pcon Register Address 087H PCON.1 Stop PCON.3EPFWPCON.2 EWT PCON.0 IDL Timer Control Register Label Tcon Register Address 088H TCON.0 IT0 Timer Mode RegisterLabel Tmod Register Address 089H Gate Serial Control Register LabelSCON Register Address 098H SCON.0 Interrupt Enable RegisterLabelIE Register Address 0A8H ET1 Interrupt Priority Register LabelIP Register Address 0B8H RNGE3±0 DS5001 CRC RegisterLabel CRC Register Address 0C1H CRC.1 MDM PA3 PA2 PA1 PA0 DS5000 Memory Control RegisterLabelMCON Register Address 0C6H RA32/8 DS5001 Mcon Register Label Mcon Register Address 0C6HMCON.0 Accessed by Movx instructions on the Byte±wide bus Program Status Word Register LabelPSW Register Address 0D0H RPCTL.7 RNR DS5001/DS5002 RPC Control RegisterLabel Rpctl Register Address 0D8H RPCTL.3 IBI RPCTL.1 Rpcon DS5001/DS5002 RPC Status RegisterLabel RPS Register Address 0DAH IA0 RPS.0 RPS.1IBF OBF ADD A, R4 Instruction SETAddressing Modes Setb 00H Acall 100H Call to the subroutine at ±20 Branch to the location PC+2 ±Addressing Address Instructions That Affect Flag Settings Program Status FlagsFlags Instruction OV AC Data Reten Part Tion Current RAM Size Vendor Memory InterconnectRecommended SRAMs for USE with Soft Microcontrollers ±1 25C 40C 70C DS5000 Series Module Block Diagram ±2 Memory Interconnect of the DS5000FP ±1 Óóóóóóóóó Ó Memory Interconnect of the Partitionable DS5001/DS5002 ±3 Óóóóóóóó 52 14Ó GND Memory Interconnect Using the 128K Sram ±5 DS2251T±128 Block Diagram ±6 DS2252T±32 Block Diagram ±7 Ôôôôôô LITHIUM/BATTERY Backup Battery Backed CircuitsData Retention Battery Lifetime Power Supply Slew Rate ±1Battery Attach Procedure Battery attached 54 * 10±3 180 * 10±32400 + 75 * 10±9 * 24 21.68 * 10±3 Lithium Battery Usage Freshness Seal CONTROL/STATUS Bits for Power Control ±1 Bit Description Power ManagementIdle Mode ªPower On Resetº PIN States in IDLE/STOP Modes ±1 Stop ModeMode Program ALE Psen Memory PCON.3 Epfw Secure Microcontroller Power Cycling Timing ±2 Voltage Monitoring Circuitry Partial Power Failures Power Fail InterruptTotal Power Failure Vpfw threshold is above the specified minimum Secure Microcontroller Power Management ±3 Reset Vector Timed Access Timed Access ±1Software Control Timed Access Protected Control Bits ±1 BIT Name Micro Version Location Description 050396 66/173 Watchdog Timer ±2 0C7H, #055H 2nd TA ValueIP.7 Watchdog Timer Control Bits CRC Memory Verification CRC.1 DS5001 CRC Register Address 0C1hRange 3±0 CRC.0 CRC Code Example ±3 This routine tests the CRC±16 circuit in the DS5001FP Security Overview FeatureFirmware Security DS5001 DS5000 DS5002 Security Lock RAM MemoryEncrypted Memory DS5000 Software Encryption Block Diagram ±1 DS5002 Software Encryption Block Diagram ±2 050396 74/173 Encryption Algorithm Encryption KeyEncryption Key Selection and Loading Dummy Bus Access Dummy BUS Access Timing ±3 Microprobe/Die Top Coating On±chip Vector RAMSelf±Destruct Input Random Number Generator Security Summary by Part DS5000FP / DS5000T / DS2250TDS5001FP / DS2251T Application Advanced Security Techniques Change Code External CircuitsTamper Protection Reset Conditions Reset SourcesReset Status Bits ±1 Special Function Register Reset States ±1 Reset Condition Reset TypeRegister Power On Reset Power on Reset Timing ±2Chanical and some time is required to get the mass No±VLI Power On Reset External ResetWatchdog Timer Reset Application Reset Routine Example Memory Interrupts TIMERS/SERIAL ProtectionMemory Map Interrupts Timed ± DS5000 only Microprocessor disables timer activity excluding TimersTively. Shown here is an example of Timer and Serial Protection Interrupt Sources Interrupt Source Enable BIT LocationInterrupts Interrupt Source Vector Address Flag Flag Location Machine cycle when the interrupts are enabled. INT0 is Timer InterruptsPower±fail Warning Interrupt External Interrupts Simulated Interrupts Interrupt Request Sources ±1 Interrupt Enable Control Bits ±2 Bit Description ET0EX0 Priority Flag Interrupt Source Interrupt PrioritiesInterrupt Priority Control Bits ±3 Bit Description IP.4 Interrupt Acknowledge Interrupt Acknowledge Sequence ±4Flag Vector Address Interrupt Source 050396 94/173 PIN Name Parallel I/O OverviewPort 0 Functional Circuitry ±1 Function Port 1 Functional Circuitry Port 2 Functional Circuitry Port 3 Functional Circuitry Output Functions Parallel Port Output Buffers Ports 1, 2, and 3 ±2 Input Function Mnemonic Description READ±MODIFY±WRITE InstructionsReprogrammable Peripheral Controller RPC Port 0 D0±7 Command USE of the RPC Mode ±3USE of the RPC Mode ±4 RPC Interrupts RPC Status Register ± Status Address 0DAH ±5 ST7 ST6 ST5 ST4 IAO IBF OBF Dbbout RPC ProtocolDMA Operation 103 RNR Exbs IBI DMA Rpcon RG0 Port 2 becomes the control signals as shown in ±3RPC Control Register ± Rpctl Address 0D8H ±6 Rpcon bit is set Programmable Timers Functional Description TMOD.6 Timer TMOD.2 TimerTmod Register Control BIT Summary ±1 Bit Description Tcon Register CONTROL/STATUS Bits ±2 TMOD.5, TMOD.4TMOD.1, TMOD.0 Scribed for TR0, TF0, and INT0 TIMER/COUNTER Mode 0 and 1 Operation ±3Mode 107 TIMER/COUNTER Mode 2 Operation ±4 108 Timer 0 Mode 3 Operation ±5 109 Serial Port Operating Modes ±1 Mode SYNC/ASYNC Baud ClockSerial I/O Function Description START/STOP Serial Port Control Register ±1 Bit Description Mode Function Word Length PeriodMode Sync Bits CLK Async Timer 1 Overflow ªXmit Bit 8º SCON.0 SCON.2 RB8SCON.1 Baud Rate Generation Smod Timer TH1 Timer 1 Baud Rate Generation ±2Synchronous Operation Mode Baud Rate BPS 114 Mode 0 Block Diagram and Timing ±2 115 Asynchronous Operation 116 Mode 2 Smod BRG Clock117 Serial Port Mode 1 Block Diagram ±3 118 MODE2 and 3 Block Diagram ±4 119 Mode Function Word Length Baud Clock Application Serial Port InitializationSerial I/O Operating Modes ET1 EX1 ET0 EX0 SM0 SM1 SM2 RENTB8 RB8 PT1 PX1 PT0 PX0 Smod POR PFW WTR Epfw EWT Stop IDL TF1 TR1 TF0 TR0IE1 IT1 IE0 123 Clock Source Input ±2 CPU Timing OscillatorCrystal Connection ±1 XTAL1 Instruction Timing 125 BYTE±WIDE RAM Instruction Execution Timing ±3 Expanded Program Memory Timing126 Expanded Program Memory Fetch ±4 127 Expanded Data Memory Read ±5 Expanded Data Memory Write ±6128 Expanded Data Memory Timing Complete RD cycle, including activation of ALE and RD129 DS5000FP DS5001/2FP Invoking the Bootstrap LoaderProgram Loading Introduction 130 Exiting the Loader DS5000 SeriesDS5001/DS5002 Series 131 132 MODEM=1 PROG=0 Serial Program Load Mode Serial Load Configuration ±2133 Crystal Freq MHz 300 1200 2400 AUTO±BAUD Rate DetectionBaud Rate 57600 Command Line Syntax Bootstrap Loader InitializationCommand Line Interface Command Function Version → 000AH AB → 00ABH Command SummariesBegin±address end±address ABC → 0ABCH Abcd → 0ABCDH Abcde → 0BCDEH Byte Byte begin±address end±addressByte±1 byte±2 byte±3 byte±4 byte±5 P0 value P1 value P2 value P3 value Mcon Xon/XoffCRC/MCON/MSL/RPCTL byte MSL Eillcmd Error Messages EargreqEextarg Eillopt Intel HEX File Format 140 Parallel Program Load Cycles ±4 Parallel Program Load Configuration ±3Parallel Program Load Operation 141 8751±COMPATIBLE Program Load Cycles ±3 Parallel Program Load ModeMode RST Psen Prog P2.7 P2.6 P2.5 Pulses specified, each with a low time of 90 to RPC Program Mode OperationParallel Programming Concerns 143 DS1215 Phantom Time Chip DS5000T/DS2250T Functional Block Diagram ±1REAL±TIME Clock 144 145 Pattern Comparison Register Description ±2 146 DS1215 Register Entry Flowchart ±3 147 Special Bits DS1215 Time Registers Description ±4Registers 148 Time Register Examples ±5 149 DS1283 Watchdog Timekeeper Chip 150 DS2251T/DS2252T RTC Block Diagram ±6 Memory MAP151 DS1283 REAL±TIME Clock Memory MAP ±7 152 DS1283 REAL±TIME Clock Command Register ±8 DS1283 RTC Interrupts Alarm Maskbit Operation ±9Alarm Condition Mask Application Using the DS5000T RTC DS1215 Example 155 Wbyte 156 RET 157 158 Application Using the DS2251T RTC DS1283 Example 159 160 161 162 163 RAM Loses Data When Powered Down TroubleshootingUnexplained Device Resets Time Microcontroller Reads the Wrong Time Unable to Invoke Stop Mode Serial Port does not WorkProgram will not Execute INT0 is Stuck LOW on DS2252T High Current Drain in Stop ModeData is Lost or Corrupted DS5000TK KIT does not Respond to KIT5K Software DOS Instruction SET Details Mnemonic Instruction Code HEX Byte Cycle Explanation DA a CLR a CPL a RR a RL aRLC a RRC a Mnemonic Instruction Code HEX Byte CPL bit Bit = bit CLR bit Bit =Setb bit Bit = ANL C, bit = C and bit RET RetiDptr NOP