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Mitsubishi DS907x SIP, DS5000TK manual Program Status Flags, Instructions That Affect Flag Settings

Models: DS5000TK DS907x SIP

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USER'S GUIDE

Program Status Flags

All of the Program Status flags are contained in the PSW register. Instructions which affect the states of the flags are summarized below.

INSTRUCTIONS THAT AFFECT FLAG SETTINGS

		FLAGS							FLAGS
INSTRUCTION	C	OV	AC	INSTRUCTION					C OV AC
ADD				CLR C					0
ADDC				CPL C
SUBB				ANL C, bit
MUL	0			ANL C,
MUL	0			ANL C,	bit
DIV	0			ORL C, bit
DA				ORL C,
DA				ORL C,		bit
RRC				MOV C, bit
RLC				CJNE
SETB C	1

LEGEND:

0 = Cleared to 0

1 = Set to a 1

= Modified according to the result of the operation.

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Mitsubishi DS907x SIP, DS5000TK manual Program Status Flags, Instructions That Affect Flag Settings, Flags Instruction OV AC

Contents

Table of Contents Introduction Software SecuritySeparate ADDRESS/DATA BUS Large Nonvolatile Memory IN±SYSTEM LoadingHigh Reliability Operation Module Description ON±BOARD Memory PackageProduct Description DS5000FP Soft Microprocessor ChipDS5000T Soft Microcontroller Module DS2250T Soft Microcontroller ModuleDS2251T 128K Soft Microcontroller Module DS5002FP Secure Microprocessor ChipDS2252T Secure Microcontroller Module Selection Guide Chip Description Maximum Speed Part NumberModule Description Speed Clock Part NumberSecure Microcontroller Architecture Secure Microcontroller Architectural Block Diagram Figure Timed Access Logic Parallel I/OProgram/Data RAM Interface High±Reliability CircuitryWatchdog Timer Resident Loader ROMProgrammers Guide Secure Microcontroller Memory OrganizationSecure Microcontroller Memory MAP ±1 Internal RegistersScratchpad Register MAP ±2 Program and Data Memory PSW.4±3 R1±R0 Register Bank SelectBank Starting Address R0 DS5000 Series Memory Organization Important Application NoteDS5000 Series Memory MAP ±3 Memory map. The first is the EA pin. The second isOverrides the condition of the EA pin as well DS5000 Memory Map Control DS5000 Series Mcon Register ±4 Bit DescriptionPA3 DS5001/DS5002 Memory Organization MCON.3RA32/8 MCON.2 ECE2RG1 RG0 Range CE1 Access CE2 Access PA3 PA2 PA1 PA0 Partition BYTE±WIDE BUS Memory MAPMsel RG1 RG0 Program Data Program Access Data Access Partitionable Memory MAP for DS5001/DS5002 Series ±5CE1 CE3 CE4 CE1 CE2 CE3NON±PARTITIONABLE Memory MAP for DS5001, DS5002 Series ±6 DS5001/DS5002 Memory Mapped PeripheralsPeripheral Enables in the Data Memory MAP ±7 DS5001/DS5002 Memory Map ControlDS5001/DS5002 Series Mcon Register ±8 PA3 PA2 PA1 PA0 RG1 PESMCON.3 RG1 MCON.2 PESLoading and Reloading Program Memory RPCTL.5 ExbsRPCTL.4 RPCTL.0 RG0050396 23/173 Reloading Portions of a DS5000 Series Device ±10 Soft Reload of a DS5001/DS5002 Reloading a DS5001/DS5002 Series Device ±11 Special Function Registers DS5000 Series Special Function Register MAP ±12 ECE2DS5001/DS5002 Series Special Function Register MAP ±13 CRCPower Control Register Label Pcon Register Address 087HPCON.3EPFW PCON.2 EWTPCON.1 Stop PCON.0 IDLTimer Control Register Label Tcon Register Address 088HTimer Mode Register Label Tmod Register Address 089HTCON.0 IT0 GateSerial Control Register LabelSCON Register Address 098HInterrupt Enable Register LabelIE Register Address 0A8HSCON.0 ET1Interrupt Priority Register LabelIP Register Address 0B8HDS5001 CRC Register Label CRC Register Address 0C1HRNGE3±0 CRC.1 MDMDS5000 Memory Control Register LabelMCON Register Address 0C6HPA3 PA2 PA1 PA0 RA32/8DS5001 Mcon Register Label Mcon Register Address 0C6HMCON.0 Accessed by Movx instructions on the Byte±wide bus Program Status Word Register LabelPSW Register Address 0D0HDS5001/DS5002 RPC Control Register Label Rpctl Register Address 0D8HRPCTL.7 RNR RPCTL.3 IBIDS5001/DS5002 RPC Status Register Label RPS Register Address 0DAHRPCTL.1 Rpcon IA0RPS.1 IBFRPS.0 OBFInstruction SET Addressing ModesADD A, R4 Setb 00H±20 Branch to the location PC+2 ± AddressingAcall 100H Call to the subroutine at AddressInstructions That Affect Flag Settings Program Status FlagsFlags Instruction OV AC Memory Interconnect Recommended SRAMs for USE with Soft Microcontrollers ±1Data Reten Part Tion Current RAM Size Vendor 25C 40C 70CDS5000 Series Module Block Diagram ±2 Memory Interconnect of the DS5000FP ±1Óóóóóóóóó Ó Memory Interconnect of the Partitionable DS5001/DS5002 ±3Óóóóóóóó 52 14Ó GND Memory Interconnect Using the 128K Sram ±5 DS2251T±128 Block Diagram ±6 DS2252T±32 Block Diagram ±7 ÔôôôôôLITHIUM/BATTERY Backup Battery Backed CircuitsData Retention Power Supply Slew Rate ±1 Battery Attach ProcedureBattery Lifetime Battery attached54 * 10±3 180 * 10±32400 + 75 * 10±9 * 24 21.68 * 10±3 Lithium Battery Usage Freshness SealPower Management Idle ModeCONTROL/STATUS Bits for Power Control ±1 Bit Description ªPower On ResetºStop Mode Mode Program ALE Psen MemoryPIN States in IDLE/STOP Modes ±1 PCON.3 EpfwSecure Microcontroller Power Cycling Timing ±2 Voltage Monitoring CircuitryPower Fail Interrupt Total Power FailurePartial Power Failures Vpfw threshold is above the specified minimumSecure Microcontroller Power Management ±3 Reset VectorTimed Access Timed Access ±1Software Control Timed Access Protected Control Bits ±1 BIT Name Micro Version Location Description050396 66/173 Watchdog Timer ±2 0C7H, #055H 2nd TA ValueIP.7 Watchdog Timer Control Bits CRC Memory VerificationDS5001 CRC Register Address 0C1h Range 3±0CRC.1 CRC.0CRC Code Example ±3 This routine tests the CRC±16 circuit in the DS5001FPFeature Firmware SecuritySecurity Overview DS5001 DS5000 DS5002Security Lock RAM MemoryEncrypted Memory DS5000 Software Encryption Block Diagram ±1 DS5002 Software Encryption Block Diagram ±2050396 74/173 Encryption Algorithm Encryption KeyEncryption Key Selection and Loading Dummy Bus Access Dummy BUS Access Timing ±3On±chip Vector RAM Self±Destruct InputMicroprobe/Die Top Coating Random Number GeneratorSecurity Summary by Part DS5000FP / DS5000T / DS2250TDS5001FP / DS2251T Application Advanced Security Techniques Change Code External CircuitsTamper Protection Reset Conditions Reset SourcesReset Status Bits ±1 Special Function Register Reset States ±1 Reset Condition Reset TypeRegister Power On Reset Power on Reset Timing ±2Chanical and some time is required to get the mass No±VLI Power On Reset External ResetWatchdog Timer Reset Application Reset Routine Example Memory Interrupts TIMERS/SERIAL ProtectionMemory Map Interrupts Timed ± DS5000 onlyTimers Tively. Shown here is an example of Timer and SerialMicroprocessor disables timer activity excluding ProtectionInterrupt Source Enable BIT Location InterruptsInterrupt Sources Interrupt Source Vector Address Flag Flag LocationTimer Interrupts Power±fail Warning InterruptMachine cycle when the interrupts are enabled. INT0 is External InterruptsSimulated Interrupts Interrupt Request Sources ±1Interrupt Enable Control Bits ±2 Bit Description ET0EX0 Interrupt Priorities Interrupt Priority Control Bits ±3 Bit DescriptionPriority Flag Interrupt Source IP.4Interrupt Acknowledge Interrupt Acknowledge Sequence ±4Flag Vector Address Interrupt Source 050396 94/173 Parallel I/O Overview Port 0 Functional Circuitry ±1PIN Name FunctionPort 1 Functional Circuitry Port 2 Functional CircuitryPort 3 Functional Circuitry Output FunctionsParallel Port Output Buffers Ports 1, 2, and 3 ±2 Input FunctionREAD±MODIFY±WRITE Instructions Reprogrammable Peripheral Controller RPCMnemonic Description Port 0 D0±7USE of the RPC Mode ±3 USE of the RPC Mode ±4Command RPC InterruptsRPC Status Register ± Status Address 0DAH ±5 ST7 ST6 ST5 ST4 IAO IBF OBFRPC Protocol DMA OperationDbbout 103Port 2 becomes the control signals as shown in ±3 RPC Control Register ± Rpctl Address 0D8H ±6RNR Exbs IBI DMA Rpcon RG0 Rpcon bit is setProgrammable Timers Functional Description TMOD.6 Timer TMOD.2 TimerTmod Register Control BIT Summary ±1 Bit Description Tcon Register CONTROL/STATUS Bits ±2 TMOD.5, TMOD.4TMOD.1, TMOD.0 TIMER/COUNTER Mode 0 and 1 Operation ±3 ModeScribed for TR0, TF0, and INT0 107TIMER/COUNTER Mode 2 Operation ±4 108Timer 0 Mode 3 Operation ±5 109Mode SYNC/ASYNC Baud Clock Serial I/O Function DescriptionSerial Port Operating Modes ±1 START/STOPMode Function Word Length Period Mode Sync Bits CLK Async Timer 1 OverflowSerial Port Control Register ±1 Bit Description ªXmit Bit 8ºSCON.2 RB8 SCON.1SCON.0 Baud Rate GenerationTimer 1 Baud Rate Generation ±2 Synchronous Operation ModeSmod Timer TH1 Baud Rate BPS114 Mode 0 Block Diagram and Timing ±2 115Asynchronous Operation 116Mode 2 Smod BRG Clock117 Serial Port Mode 1 Block Diagram ±3 118MODE2 and 3 Block Diagram ±4 119Mode Function Word Length Baud Clock Application Serial Port InitializationSerial I/O Operating Modes SM0 SM1 SM2 REN TB8 RB8ET1 EX1 ET0 EX0 PT1 PX1 PT0 PX0Smod POR PFW WTR Epfw EWT Stop IDL TF1 TR1 TF0 TR0IE1 IT1 IE0 123 CPU Timing Oscillator Crystal Connection ±1Clock Source Input ±2 XTAL1Instruction Timing 125BYTE±WIDE RAM Instruction Execution Timing ±3 Expanded Program Memory Timing126 Expanded Program Memory Fetch ±4 127Expanded Data Memory Read ±5 Expanded Data Memory Write ±6128 Expanded Data Memory Timing Complete RD cycle, including activation of ALE and RD129 Invoking the Bootstrap Loader Program Loading IntroductionDS5000FP DS5001/2FP 130DS5000 Series DS5001/DS5002 SeriesExiting the Loader 131132 MODEM=1 PROG=0Serial Program Load Mode Serial Load Configuration ±2133 AUTO±BAUD Rate Detection Baud RateCrystal Freq MHz 300 1200 2400 57600Bootstrap Loader Initialization Command Line InterfaceCommand Line Syntax Command Function VersionCommand Summaries Begin±address end±address→ 000AH AB → 00ABH ABC → 0ABCH Abcd → 0ABCDH Abcde → 0BCDEHByte begin±address end±address Byte±1 byte±2 byte±3 byte±4 byte±5Byte P0 value P1 value P2 value P3 valueXon/Xoff CRC/MCON/MSL/RPCTL byteMcon MSLError Messages Eargreq EextargEillcmd EilloptIntel HEX File Format 140Parallel Program Load Configuration ±3 Parallel Program Load OperationParallel Program Load Cycles ±4 141Parallel Program Load Mode Mode RST Psen Prog8751±COMPATIBLE Program Load Cycles ±3 P2.7 P2.6 P2.5RPC Program Mode Operation Parallel Programming ConcernsPulses specified, each with a low time of 90 to 143DS5000T/DS2250T Functional Block Diagram ±1 REAL±TIME ClockDS1215 Phantom Time Chip 144145 Pattern Comparison Register Description ±2 146DS1215 Register Entry Flowchart ±3 147DS1215 Time Registers Description ±4 RegistersSpecial Bits 148Time Register Examples ±5 149DS1283 Watchdog Timekeeper Chip 150DS2251T/DS2252T RTC Block Diagram ±6 Memory MAP151 DS1283 REAL±TIME Clock Memory MAP ±7 152DS1283 REAL±TIME Clock Command Register ±8 Alarm Maskbit Operation ±9 Alarm ConditionDS1283 RTC Interrupts MaskApplication Using the DS5000T RTC DS1215 Example 155Wbyte 156RET 157158 Application Using the DS2251T RTC DS1283 Example 159160 161 162 163 Troubleshooting Unexplained Device ResetsRAM Loses Data When Powered Down Time Microcontroller Reads the Wrong TimeUnable to Invoke Stop Mode Serial Port does not WorkProgram will not Execute High Current Drain in Stop Mode Data is Lost or CorruptedINT0 is Stuck LOW on DS2252T DS5000TK KIT does not Respond to KIT5K SoftwareDOS Instruction SET Details Mnemonic Instruction Code HEX Byte Cycle ExplanationDA a CLR a CPL aRL a RLC aRR a RRC aMnemonic Instruction Code HEX Byte CLR bit Bit = Setb bit Bit =CPL bit Bit = bit ANL C, bit = C and bitRET RetiDptr NOP