Mitsubishi DS5000TK, DS907x SIP Power Fail Interrupt, Total Power Failure, Partial Power Failures

USER'S GUIDE

Power Fail Interrupt

When VCC is stable, program execution proceeds as normal. If VCC should decay from its nominal operating voltage and drop to a level below the VPFW threshold, then the internal PFW status flag (PCON.5) will be set. In addition, a Power Fail Warning interrupt will be gener- ated if it has been enabled via the EPFW control bit (PCON.3). The purpose of these indicators is to warn the processor of a potential power failure.

The VPFW threshold is above the specified minimum

value for VCC (VCCmin) for full processor operation. The VPFW threshold is selected so that with a reasonable

power supply slew rate, ample time is allowed for the ap- plication software to save all critical information which would otherwise be lost in the absence of VCC. Such in- formation may include the states of the Accumulator, Stack Pointer, Data Pointer, and other Special Function registers which are initialized with a reset when VCC voltage is applied once again. Saved data can be placed into Scratchpad RAM or Byte±wide NV RAM. Through the use of the Power Fail Warning interrupt, an orderly shutdown of the system may be performed prior to the time that processor operation is halted in the event that VCC voltage is removed entirely.

The PFW flag is set to a logic 1 whenever the VCC level

is below the VPFW threshold. It is cleared in one of two ways: 1) a read of the PFW bit from software, or 2) a

Power On Reset. If VCC is still below the VPFW threshold when the bit is cleared, then the PFW bit will be immedi- ately set once again. An interrupt will be generated any time that both the EPFW bit and the PFW flag are set.

Total Power Failure

If VCC voltage should fall below the VCCmin threshold, processor operation will halt. This is done by first placing

the CPU in a reset condition and then stopping the inter- nal clock oscillator circuit, as illustrated in Figure 7±2. At this time the interface to the Program/Data RAM is dis-

abled by pulling the CE line high. This action guarantees an orderly shutdown for the lithium-backed RAM.

The microprocessor is automatically placed in the Data Retention state, if VCC voltage drops below VLI, the con- trol circuitry accomplishes this by switching the internal power supply line (VCCI) from pin to the lithium power source. At this time, data is retained and no power is drawn from VCC.

When power is once again applied to the system, the VCC voltage will eventually cross the VLI threshold. When this action is detected, the microprocessor will automatically switch its internal supply line from the lithi- um source back to the VCC pin. When VCC voltage

eventually goes above the VCCmin threshold, the clock oscillator is allowed to start up and an internal Power On

Reset cycle is executed. Part of the cycle involves a considerable delay that is generated to allow the clock oscillator frequency to stabilize. Activity on the RST pin is ignored until this sequence is completed. The time re-

quired for this cycle is shown as tPOR in Figure 7±2 and is specified in the AC Electrical Specifications. A de-

tailed description of the Power On reset cycle operation is given in Section 10.

Typically, the time taken for the Power On Reset cycle will be longer to complete than it takes for VCC to rise above the VPFW threshold. In this case the internal PFW flag will be reset before execution of the user's program begins as illustrated in Figure 7±2. If the Power On Re- set cycle completes before VCC>VPFW, then PFW will

be set again as a result of VCC<VPFW during user soft- ware execution. A Power Fail Interrupt will occur at this

time if the EPFW bit is enabled. A user should monitor the POR bit to know the power supply status. Refer to Figure 7±3 for details.

Partial Power Failures

Two cases of partial power failure can occur in which VCC voltage does not go through a completed power fail cycle as described above. The first case is that in which

VCC drops below the VCCmin threshold and then returns to its nominal level without going below the VLI thresh-

old. The second case is that in which VCC drops below the VPFW threshold and then returns to its nominal level

without going below the VCCmin threshold. Both of these cases are very possible in a system application and

could be caused by a ªbrownoutº condition on an AC power line.

The first case is indistinguishable by the software from the complete power fail cycle which was previously de- scribed. When VCC drops below VPFW the PFW flag will be set and the clock oscillator will be stopped when VCC

drops below VCCmin. The only operational difference is that if VCC never drops below the VLI threshold, the in-

ternal power supply line will never be switched over to the lithium cell. When VCC rises back above the VCCmin

050396 62/173

63