Mitsubishi DS5000TK, DS907x SIP manual No±VLI Power On Reset, External Reset, Watchdog Timer Reset

USER'S GUIDE

No±VLI Power On Reset

During a Power On Reset cycle, a test is automatically performed by the internal control circuitry to measure the voltage of the lithium power source. This test deter- mines whether or not the voltage (VLI) is above the mini-

mum level required (VLImin) to insure that the nonvolatile areas can be maintained in the absence of VCC. If the

voltage is found to be above the required level, then no special initialization is performed. If it is below the re- quired level, then the Special Function Registers are ini- tialized during the reset as shown in Table 10±1 for a No±VLI reset.

The additional initialization can be summarized as fol- lows:

The POR bit (PCON.6) is cleared to indicate that a Pow- er On Reset has just occurred.

The Watchdog Timer is disabled by writing a 0 into the EWT bit (PCON.2).

The Partition Address bits (PA3±0) are set to all 1's. In addition, the Range function is set to select a 32K byte address space for the RAM.

On a DS5000, the Encryption Key and software encryp- tion operation are disabled.

Finally, the Security Lock bit is cleared to 0.

External Reset

For applications which require an external reset capabil- ity, a reset pin (RST) is provided with a Schmitt Trigger input. This input may be used to force a reset condition any time when the micro is executing the application program or when it is in either the Idle or Stop modes. Reset is initiated by holding the RST pin active (high) for

a minimum time of two machine cycles (24 clock oscilla- tor periods). If the reset was initiated from Stop mode, the rising edge will result in an internally±generated Power On Reset time (tPOR) which is required for the os- cillator to start and for the clock frequency to stabilize.

All of the control bits that are initialized according to the type of reset within the Special Function registers are left unchanged from their previous condition following an External Reset. Note, an RC circuit should not be used on the reset pin to generate a power±on reset.

Watchdog Timer Reset

The on±chip Watchdog Timer is provided as a method of restoring proper software operation in the event that software control is lost. The Watchdog Timer is enabled via the EWT bit (PCON.2). This bit can only be written by using the Timed Access function.

Once the Watchdog Timer is initialized, an internal reset will be issued if the software fails to reset the timer via the RWT bit (IP.7) at least once before it reaches its timeout condition. The timeout period is equal to 122,880 machine cycles. If a 12 MHz crystal is used as the time base element, this give a timeout period of

122.88milliseconds. In order to reset the Watchdog Timer in the application software, the RWT bit must be written with a 1 using the Timed Access procedure. The Watchdog Timer is also reset following any other type of reset.

When a Watchdog Timer reset occurs, special initializa- tion is performed on the Special Function Registers as shown in Table 10±1.

The distinguishing action taken during this type of reset is that the WTR status flag is set to indicated that a Watchdog Timer Reset has just occurred.

050396 84/173

85