Mitsubishi DS907x SIP, DS5000TK manual Power On Reset, Power on Reset Timing ±2

USER'S GUIDE

Power On Reset

The Secure Microcontroller family provides an internal Power On Reset capability which requires no external components. When voltage is applied to the VCC pin from a power off condition, the device automatically per-

forms an internal reset sequence to prepare the proces- sor for execution of the application software. The tradi- tional capacitor reset circuit should not be used. Figure 10±2 illustrates the timing associated with the Power On Reset cycle.

POWER ON RESET TIMING Figure 10±2

	VCCMIN
	VLI
VCCI	tCSU

CLOCK

OSC.

INTERNAL RESET

tPOR

LITHIUM CURRENT

This cycle begins with Power On reset delay time. This is generated by the internal control circuitry to allow the internal clock oscillator to start up from its halted state

that is in effect when VCC is below VCCmin. The period tCSU is a mechanical startup time that is dependent on

the individual crystal. The delay shown as tPOR in the figure is generated by internal circuitry which counts a total of 21,504 (1.792 ms @ 12 MHz) clock oscillator pe- riods before it allows the internal reset line to be re- leased. The purpose of this delay is to allow time for the clock frequency to stabilize.

The Power On Reset delay is not the total amount of time which must pass before execution can begin in the application from the initial application of VCC voltage. First the power supply slew rate is required for VCC to

rise from 0V to the VCCmin threshold shown in Figure 10±2. Next, operation with a crystal is partly me-

chanical and some time is required to get the mass of

the crystal into vibrational motion. The user should con- sult the crystal vendor for a start±up time specification.

When a Power On Reset cycle is in progress, the exter- nal RST pin has no effect on internal operation. Once control of the processor is transferred to the user's pro- gram, a hardware reset may be issued externally via the RST pin.

A Power On Reset causes special initialization to be performed on the Special Function Registers as shown in Table 10±1.

The distinguishing action taken during a Power On Re- set is that the POR bit is cleared in order to indicate that a Power On Reset has just occurred. All other control bits which are initialized according to the type of reset are left unchanged from their previous condition.

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