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Mitsubishi DS5000TK, DS907x SIP manual Reti, Dptr

Models: DS5000TK DS907x SIP

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USER'S GUIDE

MNEMONIC

INSTRUCTION CODE

HEX

BYTE

CYCLE

EXPLANATION

D7

D6

D5

D4

D3

D2

D1

D0

ACALL addr 11

a10

a9

a8

1

0

0

0

1

Byte 1

2

2

(PC) = (PC) + 2

a7

a6

a5

a4

a3

a2

a1

a0

Byte 2

(SP) = (SP) + 1

((SP)) = (PC7±0)

(SP) = (SP) + 1

((SP)) = (PC15±8)

(PC)=page address

LCALL addr 16

0

0

0

1

0

0

1

0

12

3

2

(PC) = (PC) + 3

a15

a14

a13

a12

a11

a10

a9

a8

Byte 2

(SP) = (SP) + 1

a7

a6

a5

a4

a3

a2

a1

a0

Byte 3

((SP)) = (PC7±0)

(SP) = (SP) + 1

((SP)) = (PC15±8)

(PC) = addr15±0

RET

0

0

1

0

0

0

1

0

22

1

2

(PC15±8) = ((SP))

(SP) = (SP) ± 1

(PC7±0) = ((SP))

(SP) = (SP) ± 1

BRANCHING

RETI

0

0

1

1

0

0

1

0

32

1

2

(PC15±8) = ((SP))

(SP) = (SP) ± 1

(PC7-0) = ((SP))

(SP) = (SP) ± 1

AJMP addr 11

a10

a9

a8

0

0

0

0

1

Byte 1

2

2

(PC) = (PC) + 2

PROGRAM

a

a

a

a

a

a

a

a

Byte 2

(PC10-0) =

a15

a14

a13

a12

a11

a10

a9

a8

Byte 2

7

6

5

4

3

2

1

0

page addr

LJMP addr 16

0

0

0

0

0

0

1

0

02

3

2

(PC) = addr15-0

a7

a6

a5

a4

a3

a2

a1

a0

Byte 3

SJMP rel

1

0

0

0

0

0

0

0

80

2

2

(PC) = (PC) + 2

r7

r6

r5

r4

r3

r2

r1

r0

Byte 2

(PC) = (PC) + rel

JMP @A +

0

1

1

1

0

0

1

1

73

1

2

(PC) = (A) +

DPTR

(DPTR)

JZ rel

0

1

1

0

0

0

0

0

60

2

2

(PC) = (PC) + 2

r7

r6

r5

r4

r3

r2

r1

r0

Byte 2

IF (A) = 0 THEN

(PC) = (PC) + rel

JNZ rel

0

1

1

1

0

0

0

0

70

2

2

(PC) = (PC) + 2

r7

r6

r5

r4

r3

r2

r1

r0

Byte 2

IF (A) 0 THEN

(PC) = (PC) + rel

JC rel

0

1

0

0

0

0

0

0

40

2

2

(PC) = (PC) + 2

r7

r6

r5

r4

r3

r2

r1

r0

Byte 2

IF (C) = 1 THEN

(PC) = (PC) + rel

JC rel

0

1

0

0

0

0

0

0

40

2

2

(PC) = (PC) + 2

r7

r6

r5

r4

r3

r2

r1

r0

Byte 2

IF (C) = 1 THEN

(PC) = (PC) + rel

JNC rel

0

1

0

1

0

0

0

0

50

2

2

(PC) = (PC) + 2

r7

r6

r5

r4

r3

r2

r1

r0

Byte 2

IF (C) 0 THEN

(PC) = (PC) + rel

JB bit, rel

0

0

1

0

0

0

0

0

20

3

2

(PC) = (PC) + 3

b7

b6

b5

b4

b3

b2

b1

b0

Byte 2

IF (bit) = 1 THEN

r7

r6

r5

r4

r3

r2

r1

r0

Byte 3

(PC) = (PC) + rel

050396 172/173

173

Image 173

Mitsubishi DS5000TK, DS907x SIP manual Reti, Dptr

Contents

Table of Contents Separate ADDRESS/DATA BUS IntroductionSoftware Security IN±SYSTEM Loading Large Nonvolatile MemoryHigh Reliability Operation Module Description ON±BOARD Memory PackageDS5000FP Soft Microprocessor Chip Product DescriptionDS5000T Soft Microcontroller Module DS2250T Soft Microcontroller ModuleDS2252T Secure Microcontroller Module DS2251T 128K Soft Microcontroller ModuleDS5002FP Secure Microprocessor Chip Chip Description Maximum Speed Part Number Selection GuideModule Description Speed Clock Part NumberSecure Microcontroller Architecture Secure Microcontroller Architectural Block Diagram Figure Parallel I/O Timed Access LogicProgram/Data RAM Interface High±Reliability CircuitryResident Loader ROM Watchdog TimerSecure Microcontroller Memory Organization Programmers GuideSecure Microcontroller Memory MAP ±1 Internal RegistersScratchpad Register MAP ±2 Bank Starting Address R0 Program and Data MemoryPSW.4±3 R1±R0 Register Bank Select Important Application Note DS5000 Series Memory OrganizationOverrides the condition of the EA pin as well DS5000 Series Memory MAP ±3Memory map. The first is the EA pin. The second is PA3 DS5000 Memory Map ControlDS5000 Series Mcon Register ±4 Bit Description MCON.3 DS5001/DS5002 Memory OrganizationRA32/8 MCON.2 ECE2PA3 PA2 PA1 PA0 Partition BYTE±WIDE BUS Memory MAP RG1 RG0 Range CE1 Access CE2 AccessPartitionable Memory MAP for DS5001/DS5002 Series ±5 Msel RG1 RG0 Program Data Program Access Data AccessCE1 CE3 CE4 CE1 CE2 CE3DS5001/DS5002 Memory Mapped Peripherals NON±PARTITIONABLE Memory MAP for DS5001, DS5002 Series ±6DS5001/DS5002 Memory Map Control Peripheral Enables in the Data Memory MAP ±7PA3 PA2 PA1 PA0 RG1 PES DS5001/DS5002 Series Mcon Register ±8MCON.3 RG1 MCON.2 PESRPCTL.5 Exbs Loading and Reloading Program MemoryRPCTL.4 RPCTL.0 RG0050396 23/173 Reloading Portions of a DS5000 Series Device ±10 Soft Reload of a DS5001/DS5002 Reloading a DS5001/DS5002 Series Device ±11 Special Function Registers ECE2 DS5000 Series Special Function Register MAP ±12CRC DS5001/DS5002 Series Special Function Register MAP ±13Label Pcon Register Address 087H Power Control RegisterPCON.2 EWT PCON.3EPFWPCON.1 Stop PCON.0 IDLLabel Tcon Register Address 088H Timer Control RegisterLabel Tmod Register Address 089H Timer Mode RegisterTCON.0 IT0 GateLabelSCON Register Address 098H Serial Control RegisterLabelIE Register Address 0A8H Interrupt Enable RegisterSCON.0 ET1LabelIP Register Address 0B8H Interrupt Priority RegisterLabel CRC Register Address 0C1H DS5001 CRC RegisterRNGE3±0 CRC.1 MDMLabelMCON Register Address 0C6H DS5000 Memory Control RegisterPA3 PA2 PA1 PA0 RA32/8MCON.0 DS5001 Mcon RegisterLabel Mcon Register Address 0C6H Accessed by Movx instructions on the Byte±wide bus LabelPSW Register Address 0D0H Program Status Word RegisterLabel Rpctl Register Address 0D8H DS5001/DS5002 RPC Control RegisterRPCTL.7 RNR RPCTL.3 IBILabel RPS Register Address 0DAH DS5001/DS5002 RPC Status RegisterRPCTL.1 Rpcon IA0IBF RPS.1RPS.0 OBFAddressing Modes Instruction SETADD A, R4 Setb 00HAddressing ±20 Branch to the location PC+2 ±Acall 100H Call to the subroutine at AddressFlags Instruction OV AC Instructions That Affect Flag SettingsProgram Status Flags Recommended SRAMs for USE with Soft Microcontrollers ±1 Memory InterconnectData Reten Part Tion Current RAM Size Vendor 25C 40C 70CMemory Interconnect of the DS5000FP ±1 DS5000 Series Module Block Diagram ±2Memory Interconnect of the Partitionable DS5001/DS5002 ±3 Óóóóóóóóó ÓÓóóóóóóó 52 14Ó GND Memory Interconnect Using the 128K Sram ±5 DS2251T±128 Block Diagram ±6 Ôôôôôô DS2252T±32 Block Diagram ±7Data Retention LITHIUM/BATTERY BackupBattery Backed Circuits Battery Attach Procedure Power Supply Slew Rate ±1Battery Lifetime Battery attached2400 + 75 * 10±9 * 24 21.68 * 10±3 54 * 10±3180 * 10±3 Freshness Seal Lithium Battery UsageIdle Mode Power ManagementCONTROL/STATUS Bits for Power Control ±1 Bit Description ªPower On ResetºMode Program ALE Psen Memory Stop ModePIN States in IDLE/STOP Modes ±1 PCON.3 EpfwVoltage Monitoring Circuitry Secure Microcontroller Power Cycling Timing ±2Total Power Failure Power Fail InterruptPartial Power Failures Vpfw threshold is above the specified minimumReset Vector Secure Microcontroller Power Management ±3Software Control Timed AccessTimed Access ±1 BIT Name Micro Version Location Description Timed Access Protected Control Bits ±1050396 66/173 IP.7 Watchdog Timer ±20C7H, #055H 2nd TA Value CRC Memory Verification Watchdog Timer Control BitsRange 3±0 DS5001 CRC Register Address 0C1hCRC.1 CRC.0This routine tests the CRC±16 circuit in the DS5001FP CRC Code Example ±3Firmware Security FeatureSecurity Overview DS5001 DS5000 DS5002Encrypted Memory Security LockRAM Memory DS5002 Software Encryption Block Diagram ±2 DS5000 Software Encryption Block Diagram ±1050396 74/173 Encryption Key Selection and Loading Encryption AlgorithmEncryption Key Dummy BUS Access Timing ±3 Dummy Bus AccessSelf±Destruct Input On±chip Vector RAMMicroprobe/Die Top Coating Random Number GeneratorDS5001FP / DS2251T Security Summary by PartDS5000FP / DS5000T / DS2250T Application Advanced Security Techniques Tamper Protection Change CodeExternal Circuits Reset Status Bits ±1 Reset ConditionsReset Sources Register Special Function Register Reset States ±1Reset Condition Reset Type Chanical and some time is required to get the mass Power On ResetPower on Reset Timing ±2 Watchdog Timer Reset No±VLI Power On ResetExternal Reset Memory Map Application Reset Routine ExampleMemory Interrupts TIMERS/SERIAL Protection Timed ± DS5000 only InterruptsTively. Shown here is an example of Timer and Serial TimersMicroprocessor disables timer activity excluding ProtectionInterrupts Interrupt Source Enable BIT LocationInterrupt Sources Interrupt Source Vector Address Flag Flag LocationPower±fail Warning Interrupt Timer InterruptsMachine cycle when the interrupts are enabled. INT0 is External InterruptsInterrupt Request Sources ±1 Simulated InterruptsEX0 Interrupt Enable Control Bits ±2 Bit DescriptionET0 Interrupt Priority Control Bits ±3 Bit Description Interrupt PrioritiesPriority Flag Interrupt Source IP.4Flag Vector Address Interrupt Source Interrupt AcknowledgeInterrupt Acknowledge Sequence ±4 050396 94/173 Port 0 Functional Circuitry ±1 Parallel I/O OverviewPIN Name FunctionPort 2 Functional Circuitry Port 1 Functional CircuitryOutput Functions Port 3 Functional CircuitryInput Function Parallel Port Output Buffers Ports 1, 2, and 3 ±2Reprogrammable Peripheral Controller RPC READ±MODIFY±WRITE InstructionsMnemonic Description Port 0 D0±7USE of the RPC Mode ±4 USE of the RPC Mode ±3Command RPC InterruptsST7 ST6 ST5 ST4 IAO IBF OBF RPC Status Register ± Status Address 0DAH ±5DMA Operation RPC ProtocolDbbout 103RPC Control Register ± Rpctl Address 0D8H ±6 Port 2 becomes the control signals as shown in ±3RNR Exbs IBI DMA Rpcon RG0 Rpcon bit is setTmod Register Control BIT Summary ±1 Bit Description Programmable Timers Functional DescriptionTMOD.6 Timer TMOD.2 Timer TMOD.1, TMOD.0 Tcon Register CONTROL/STATUS Bits ±2TMOD.5, TMOD.4 Mode TIMER/COUNTER Mode 0 and 1 Operation ±3Scribed for TR0, TF0, and INT0 107108 TIMER/COUNTER Mode 2 Operation ±4109 Timer 0 Mode 3 Operation ±5Serial I/O Function Description Mode SYNC/ASYNC Baud ClockSerial Port Operating Modes ±1 START/STOPMode Sync Bits CLK Async Timer 1 Overflow Mode Function Word Length PeriodSerial Port Control Register ±1 Bit Description ªXmit Bit 8ºSCON.1 SCON.2 RB8SCON.0 Baud Rate GenerationSynchronous Operation Mode Timer 1 Baud Rate Generation ±2Smod Timer TH1 Baud Rate BPS114 115 Mode 0 Block Diagram and Timing ±2116 Asynchronous Operation117 Mode 2Smod BRG Clock 118 Serial Port Mode 1 Block Diagram ±3119 MODE2 and 3 Block Diagram ±4Serial I/O Operating Modes Mode Function Word Length Baud ClockApplication Serial Port Initialization TB8 RB8 SM0 SM1 SM2 RENET1 EX1 ET0 EX0 PT1 PX1 PT0 PX0IE1 IT1 IE0 Smod POR PFW WTR Epfw EWT Stop IDLTF1 TR1 TF0 TR0 123 Crystal Connection ±1 CPU Timing OscillatorClock Source Input ±2 XTAL1125 Instruction Timing126 BYTE±WIDE RAM Instruction Execution Timing ±3Expanded Program Memory Timing 127 Expanded Program Memory Fetch ±4128 Expanded Data Memory Read ±5Expanded Data Memory Write ±6 129 Expanded Data Memory TimingComplete RD cycle, including activation of ALE and RD Program Loading Introduction Invoking the Bootstrap LoaderDS5000FP DS5001/2FP 130DS5001/DS5002 Series DS5000 SeriesExiting the Loader 131MODEM=1 PROG=0 132133 Serial Program Load ModeSerial Load Configuration ±2 Baud Rate AUTO±BAUD Rate DetectionCrystal Freq MHz 300 1200 2400 57600Command Line Interface Bootstrap Loader InitializationCommand Line Syntax Command Function VersionBegin±address end±address Command Summaries→ 000AH AB → 00ABH ABC → 0ABCH Abcd → 0ABCDH Abcde → 0BCDEHByte±1 byte±2 byte±3 byte±4 byte±5 Byte begin±address end±addressByte P0 value P1 value P2 value P3 valueCRC/MCON/MSL/RPCTL byte Xon/XoffMcon MSLEextarg Error Messages EargreqEillcmd Eillopt140 Intel HEX File FormatParallel Program Load Operation Parallel Program Load Configuration ±3Parallel Program Load Cycles ±4 141Mode RST Psen Prog Parallel Program Load Mode8751±COMPATIBLE Program Load Cycles ±3 P2.7 P2.6 P2.5Parallel Programming Concerns RPC Program Mode OperationPulses specified, each with a low time of 90 to 143REAL±TIME Clock DS5000T/DS2250T Functional Block Diagram ±1DS1215 Phantom Time Chip 144145 146 Pattern Comparison Register Description ±2147 DS1215 Register Entry Flowchart ±3Registers DS1215 Time Registers Description ±4Special Bits 148149 Time Register Examples ±5150 DS1283 Watchdog Timekeeper Chip151 DS2251T/DS2252T RTC Block Diagram ±6Memory MAP 152 DS1283 REAL±TIME Clock Memory MAP ±7DS1283 REAL±TIME Clock Command Register ±8 Alarm Condition Alarm Maskbit Operation ±9DS1283 RTC Interrupts Mask155 Application Using the DS5000T RTC DS1215 Example156 Wbyte157 RET158 159 Application Using the DS2251T RTC DS1283 Example160 161 162 163 Unexplained Device Resets TroubleshootingRAM Loses Data When Powered Down Time Microcontroller Reads the Wrong TimeProgram will not Execute Unable to Invoke Stop ModeSerial Port does not Work Data is Lost or Corrupted High Current Drain in Stop ModeINT0 is Stuck LOW on DS2252T DS5000TK KIT does not Respond to KIT5K SoftwareDOS Mnemonic Instruction Code HEX Byte Cycle Explanation Instruction SET DetailsCLR a CPL a DA aRLC a RL aRR a RRC aMnemonic Instruction Code HEX Byte Setb bit Bit = CLR bit Bit =CPL bit Bit = bit ANL C, bit = C and bitDptr RETReti NOP