Mitsubishi DS5000TK CRC Code Example ±3, This routine tests the CRC±16 circuit in the DS5001FP

USER'S GUIDE

CRC CODE EXAMPLE Figure 8±3

		This routine tests the CRC±16 circuit in the DS5001FP
crcmsb	equ	0C3h
crclsb	equ	0C2h
	org	00h		;after reset, CRC regs = 0000
begin:
	mov	p2,crcmsb		;p2=00 read crcmsb register
	mov	p3,crclsb		;p3=00 read crclsb register
	mov	crclsb, #075h		;check crc register operation
				;data in = 75 result = E7C1
	mov	crclsb, #08Ah		;data in = 8A result = 37A7
	mov	crclsb, #00Bh		;data in = 0B result = 7D37
	mov	crclsb, #075h		;data in = 75 result = 31FD
	mov	crclsb, #0C7h		;data in = C7 result = 13B1
	mov	crclsb, #0AAh		;data in = AA result = 0B53
	mov	crclsb, #075h		;data in = 75 result = DA8A
	mov	crclsb, #0C7h		;data in = C7 result = 351A
	mov	crclsb, #055h		;data in = 55 result = F474
	mov	crclsb, #043h		;data in = 43 result = D6B5
	nop			;delay after last write and before first read
				;let CRC finish
	mov	p0 ,crcmsb		;p0=D6 read CRCMSB register
	mov	p1 ,crclsb		;p1=B5 read CRCLSB register
	mov	crclsb	,crclsb	;clear CRC, data in = B5 result = 00D6
	nop			;need delay
	mov	crclsb	,crclsb	;cleared, data in = D6 result = 0000
	nop
	mov	p2 ,crcmsb		;p1=00 read crcmsb register
	mov	p3 ,crclsb		;p1=00 read crclsb register
end_loop:
	sjmp	$
	end

As mentioned, the CRC±16 function is optionally avail-	After a delay of one instruction cycle, the 16±bit result
able to the application software. This is available	will be available at 0C3h and 0C2h. The CRC±16 is a
regardless of whether the automatic power±on CRC is	superior method of checking the file validity compared
used. Although a CRC could be computed completely in	to a checksum. Using the DS5001 hardware, it can be
software, it would take much longer than using the	computed quickly. When using the CRC±16 hardware
DS5001 facility. Using the CRC±16 hardware, the	as part of an application, the existing CRC should first
DS5001 series can perform a CRC±16 on 64K bytes of	be cleared. This is done by writing the CRC back on
memory in approximately 500 ms. The CRC±16 logic	itself. This process makes the CRC±16 result equal to
resides behind the two SFRs mentioned above. These	0000h. The LSB is written back twice with a delay in
display the current CRC result and also serve as the	between for computation. The code example shown in
input locations. The software must sequentially write the	Figure 8±3 displays the CRC±16 result on ports 0 and 1.
memory values into the CRC LSB at location 0C2h.

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