Main
Trademarks
Notice
Limited and Restricted Rights Legend
Contents
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List of Tables
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List of Figures
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About this Manual
Overview of Contents
Abbreviations
This document uses the following abbreviations:
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Conventions
The following table describes the conventions used throughout this manual.
Summary of Changes
The following changes have been made to this manual.
Comments and Suggestions
Safety Notes
EMC
Operation
Configuration Switches/Jumpers
Installation
Cabling and Connectors
Environment
Battery
Sicherheitshinweise
EMV
Operation
Schaltereinstellungen/Jumper
Installation
Kabel und Stecker
Umweltschutz
Batterie
Introduction
1.1 Features
1.2 Standard Compliances
The CPCI-6115 is designed to be CE compliant and to meet the following standard requirements.
Table 1-1 CPCI-6115 Features (continued)
Table 1-2 Board Standard Compliances
1.3 Ordering Information
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Hardware Preparation and Installation
2.1 Overview
2.2 Unpacking and Inspecting the Board
2.3 Environmental, Power, and Thermal Requirements
2.3.1 Environmental Requirements
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2.3.2 Power Requirements
2.3.3 Thermal Requirements
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Hardware Preparation and Installation Thermal Requirements
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Figure 2-1 CPCI-6115 Thermally Significant Components (Primary Side)
2.4 Getting Started
2.4.1 Overview of Start-up Procedure
2.4.2 Equipment Required
2.5 Baseboard Preparation
2.5.1 Configuring the Hardware
2.5.2 Setting Switches and Jumpers
2.5.3 J6, Bus Mode Selection
2.5.4 J9, Standalone Operating Mode
2.5.5 J10, Flash Bank Selection
2.5.6 J15, +/-12 V Present Header
2.5.7 J20, Safe Start Header
2.5.8 J25, SROM Initialization Enable Header
2.5.9 J99, Flash Bank A Programming Enable Header
2.5.10 SW2, Geographic Address
2.6 Operating Modes
2.7 Installing Hardware
2.7.1 Installing PMC Modules on the CPCI-6115
Procedure
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2.7.2 Installing the CPCI-6115 Baseboard
2.8 Connecting to a Console Port
2.9 Applying Power
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Controls, LEDs, and Connectors
3.1 Overview
Controls, LEDs, and Connectors Board Layout
50
3.2 Board Layout
3.3 Front Panel Connectors and LEDs
The CPCI-6115 CPU board provides these status LEDs visible on the front panel of the CPCI- 6115.
Figure 3-1 Component Layout
Table 3-1 Front Panel LEDs
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3.4 ABORT/Reset Switch
3.5 On-Board Connectors and Headers
3.5.1 J19, Front Panel Asynchronous Serial Port
3.5.2 J95, Front Panel 10/100/1000 Megabits/s Ethernet Connector
3.5.3 CompactPCI J1/J2 Connectors
3.5.4 CompactPCI Bus Connector
Pinouts for the J1 CompactPCI Bus connector on the CPCI-6115 are as follows:
Pinouts for the J2 CompactPCI Bus connector on the CPCI-6115 are as follows:
3.5.5 CompactPCI Bus Connector
Table 3-4 CompactPCI Connector, J1
3.5.6 CompactPCI User I/O Connector
3.5.7 CompactPCI Connector
Table 3-6 User I/O Connector Pinout, J3 (continued)
3.5.8 CompactPCI User I/O Connector
Asynchronous Serial Ports 1-2, TTL Levels:
3.5.9 PCI Mezzanine Card (PMC) Connectors
PCI_RSVD = PCI Reserved pin.
Table 3-9 PMC ConnectorPin Assignments, J12/J22
Table 3-8 PMC Connector Pin Assignments, J11/J21 (continued)
Table 3-10 PMC Connector Pin Assignments, J13/J23
Table 3-9 PMC ConnectorPin Assignments, J12/J22 (continued)
Table 3-11 PMC Connector Pin Assignments , J14/J24
Table 3-10 PMC Connector Pin Assignments, J13/J23 (continued)
3.5.10 Boundary Scan JTAG Header
3.5.11 Processor JTAG/COP Header
3.5.12 Stand-Alone Operation Select Header
3.5.13 Flash Boot Bank Select Header
3.5.14 Safe Start Header
3.5.15 Bus Mode Select Header
3.5.16 SROM Initialization Enable Header
3.5.17 Flash Bank A Write Protect Header
3.5.18 +/-12 V Present Header
Functional Description
4.1 Overview
Functional Description Block Diagram
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4.2 Block Diagram
4.3 General Description
4.3.1 Processor Bus Resources
4.3.2 Processor
4.3.3 L3 Cache
4.3.4 MV64360 System Controller
4.3.4.1 MV64360 CPU Bus Interface
4.3.4.2 MV64360 DDR SDRAM Interface
4.3.4.3 MV64360 32-bit Interface to Devices
4.3.4.4 MV64360 Dual PCI/PCI-X Interfaces
4.3.4.5 MV64360 Integrated Gigabit Ethernet MACs
4.3.4.6 MV64360 Integrated 2 Megabit SRAM
4.3.4.7 MV64360 General-Purpose 32-bit Timer/Counters
4.3.4.8 MV64360 Watchdog Timer
4.3.4.9 MV64360 I2O Message Unit
4.3.4.10 MV64360 Four-Channel Independent DMA Controller
4.3.4.12 Interrupt Controller
4.3.4.13 PCI Bus Arbitration
4.3.4.14 Board Reset Logic
4.3.4.15 MV64360 MPP Configuration
4.3.4.16 MV64360 Reset Configuration
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Table 4-3 MV64360 Power-Up Configuration Settings (continued)
4.3.5 System Memory
4.3.6 Flash Memory
4.3.7 NVRAM, Real-Time Clock, Watchdog Timer
4.3.8 TL16C550C UART Devices
4.3.9 System Registers
4.3.10 Serial EEPROM Devices
4.3.11 PCI Bus 0.0
4.3.12 PCI Bus 1.0
4.3.13 IDE Controller
4.3.14 Intel 21555 PCI-to-PCI Bridge
4.3.15 CompactPCI Bus
4.3.16 PMC Slots
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4.4 Miscellaneous
4.4.1 Clock Generation
4.4.2 Interrupt Handling
4.4.2.1 MV64360 Interrupt Controller
4.4.2.2 Sources of Reset
4.4.2.3 Machine Check
4.4.2.4 Soft Reset
4.4.2.5 SMI
4.4.3 Onboard Power Supplies
4.4.4 Hot Swap Support
4.4.5 Hot Swap Process
4.4.6 Intel 21555 Hot Swap Support
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Installation
5.1 Overview
Transition Module Preparation and Installation Block Diagram
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5.2 Block Diagram
5.3 Preparing the Transition Module
5.4 Rear Panel Connectors
5.5 On-Board Connectors and Headers
5.5.1 IDE CompactFlash Connector
5.5.2 PMC I/O Module Connectors
5.5.2.1 Host IO Connectors
Table 5-4 PMC I/O Module 1 - Host I/O Connector Pin Assignments, J10
Table 5-5 PMC I/O Module 2 - Host I/O Connector Pin Assignments, J20
Table 5-4 PMC I/O Module 1 - Host I/O Connector Pin Assignments, J10 (continued)
5.5.2.2 PMC I/O Connectors
Table 5-5 PMC I/O Module 2 - Host I/O Connector Pin Assignments, J20 (continued)
Table 5-6 PMC I/O Modules 1 and 2 - PMC I/O Connector Pin Assignments, J14/24
5.5.3 CompactPCI User I/O Connector
Table 5-6 PMC I/O Modules 1 and 2 - PMC I/O Connector Pin Assignments, J14/24 (continued)
Table 5-7 User I/O Connector Pinout, J3
5.5.4 CompactPCI User I/O Connector
Table 5-8 User I/O Connector Pinout, J5 (continued)
5.5.5 10/100/1000BaseTx Connectors
5.5.6 COM1 And COM2 Connectors (MXP Version)
5.5.7 RJ-45 to DB-9 Adapter for COM1 to PC COM1
5.6 Jumper Settings
5.6.1 CompactFlash Jumper
5.6.2 COM1 and COM2 Asynchronous Serial Ports Jumpers
5.7 Functional Description
5.7.1 IDE Flash
5.7.2 Ethernet Interface (CompactPCI Version)
5.7.3 Hot-Swap Support
5.7.4 Serial EEPROM
5.7.5 PMC I/O Modules
5.7.6 Asynchronous Serial Ports
5.7.6.1 I/O Signal Multiplexing (IOMX)
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5.7.6.2 Serial Port Redirection
5.7.6.3 Asynchronous Serial Port Diagrams
Transition Module Preparation and Installation PMC I/O Module
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5.7.7 PMC I/O Module
Figure 5-7 CPCI-6115-MCPTM Serial Ports 1 and 2
5.7.8 PMC I/O Module Form Factor
5.7.9 PMC I/O Connector
5.7.10 Host I/O Connector
5.7.11 PMC I/O Module Presence Detection and Identification
5.8 Installing the PIM
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5.9 Installing the Transition Module
5.10 Removing the Transition Module in a Hot-Swap Chassis
Remote Start via the PCI Bus
6.1 Overview
6.2 Register Description
6.3 Command/Response Register Description
MOTLoad Firmware
7.1 Overview
7.2 MOTLoad Description
7.3 MOTLoad Implementation and Memory Requirements
7.4 MOTLoad Commands
7.5 MOTLoad Utility Applications
7.6 MOTLoad Tests
7.7 Using MOTLoad
7.7.1 Command Line Interface
7.7.2 Command Line Help
7.7.3 Command Line Rules
7.8 MOTLoad Command List
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Memory Maps
8.1 Overview
8.2 Memory Maps
8.2.1 Default Processor Memory Map
8.2.2 Processor Memory Map
8.2.3 Default PCI Memory Map
1. This may be Flash Bank A or B depending on Flash Boot Bank Select jumper.
8.2.4 Suggested PCI Memory Map
Table 8-3 Default PCI Address Map (continued)
Table 8-4 Suggested PCI Memory Map
8.2.5 System I/O Memory Map
8.2.6 PCI Local Bus Memory Map
8.2.7 CompactPCI Memory Map
8.2.8 Address Decoding with the 21555
8.2.9 L1, L2 and L3 Cache
8.2.10 System Memory
A
A.1 Embedded Communications Computing Documents
A.2 Manufacturers Documents
A.3 Related Specifications
Table A-2 Manufacturers Documents (continued)
Table A-3 Related Specifications
Table A-3 Related Specifications (continued)
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Index
Numerics
A
C
D
R
S
T