Motorola CPCI-6115 manual Command/Response Register Description, Remote Start via the PCI Bus, 116

Models: CPCI-6115

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Remote Start via the PCI Bus

Command/Response Register Description

 

 

MOTLoad uses certain areas of memory and I/O devices for its own operation. This interface allows the host CPU to write and read any location on the local CPU bus including those in use by the firmware. Host CPUs should interrogate the firmware via the memory size query command (as described in Opcode 0x05: Memory size Query in Appendix B of the MOTLoad Firmware Packager User’s Manual) and avoid overwriting memory which is in-use by firmware; otherwise, erratic behavior may result.

6.3Command/Response Register Description

The Intel 2155x SCRATCH7 register is used as the command/response register. In this register description, and the following command descriptions, references to the upper half of the register refer to bits 0 through 15, and references to the lower half of the register refer to bits 16 through 31.

Format of command/response register (Intel 2155x SCRATCH7):

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

O Command opcode E Command Options Command Data/Result

WR

NR

At reset, hardware clears this register. After reset, firmware writes this register with the value 0x80525354. This value indicates that a reset event has occurred and the interface is ready to accept commands.

Bit Number

Description

 

 

Bit 0

The ownership flag (OWN). A value of 1 indicates the’host’ owns the

 

register. A value of 0 indicates that the local CPU owns the register.

 

 

Bits 1 to 7

7 bit command opcode field. Each command is described in more detail in

 

the MOTLoad Firmware Package User’s Manual.

 

 

Bit 8

Global error status flag (ERR). If the command completed successfully,

 

then this bit is written with the value 0 at command completion. If the

 

command fails, it will be written with the value 1. Additional command

 

specific error status may be returned in other fields of the register.

 

 

Bits 9 to 15

7 bit command option field. Each command specifies the particular

 

meaning of each of the command option bits. Option bits that are unused

 

are considered reserved and should be written to 0 to ensure compatibility

 

with future implementations of this interface.

 

For most commands, bit 9 is used to specify verbose/non-verbose mode

 

target command processing. In verbose mode, command related

 

information is printed on the target console as the host command is

 

processed. Verbose mode is selected when bit 9=0, non-verbose mode is

 

set when bit 9=1.

 

 

Bits 16 to 31

16 bit data/result field. The meaning of this field is specific to each

 

command opcode. Refer to the MOTLoad Firmware Package User’s

 

Manual for error codes.

 

 

116

CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)

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Motorola CPCI-6115 manual Command/Response Register Description, Remote Start via the PCI Bus, Bit Number Description, 116