Motorola CPCI-6115 8 TL16C550C Uart Devices, System Registers, Serial Eeprom Devices, PCI Bus

TL16C550C UART Devices Functional Description

4.3.8TL16C550C UART Devices

The CPCI-6115 board contains two Texas Instruments TL16C550C UART devices connected to the MV64360 device controller bus to provide asynchronous serial communication ports. Serial port COM1 can be routed to connector J5 for rear-panel I/O, or through EIA-232 drivers and receivers to an RJ-45 connector on the front panel. When used with a rear transition module (RTM), the routing is selectable via a jumper on the RTM. When routed to J5, the COM1 signals are TTL-level signals. The TTL-level signals for serial port COM2 are routed only to connector J5. Both ports are wired as DTE and have a maximum data rate of 115 Kbaud. A 1.8432 MHz oscillator provides the reference clock for the UARTs. The external (front-panel) signals for COM1 are ESD protected.

4.3.9System Registers

The CPCI-6115 provides all of the system registers specified in the MCPN905 CompactPCI Single Board Computer Programmer’s Reference Guide, listed in Appendix A, Related Documentation. Refer to that document for additional details.

4.3.10Serial EEPROM Devices

The CPCI-6115 board contains three 8 KB serial EEPROM devices onboard: one provides Vital Product Data (VPD) storage of the module hardware configuration, one provides storage for user configuration data, and the third (optional) provides initialization information for the MV64360 device.

The CPCI-6115 also has up to two 256-byte serial EEPROM devices onboard. These 256-byte devices provide for Serial Presence Detect (SPD) configuration information for the banks of DDR SDRAM. One SPD device is used to define the characteristics of banks 0 and 2 since these (stacked) banks must be identical. A separate SPD devices is used for bank 1. The contents of the 256-byte devices are accessed using standard one-byte addressing.

4.3.11PCI Bus 0.0

On the CPCI-6115, PCI Bus 0.0 is connected only to PMC 2 and will support 32/64-bit transfers at 66/133 MHz PCI-X or 33/66 MHz PCI.

PCI bus 0.0 is compliant to PCI-X Revision 1.0a and PCI Revision 2.2. VIO is user-selectable between +3.3 V and +5 V by positioning the PMC2 keying pin at the +3.3 V or +5 V site.

4.3.12PCI Bus 1.0

On the CPCI-6115, PCI Bus 1.0 is connected to PMC 1, the CMD PCI646U2 IDE controller and the Intel 21555 PCI-to-PCI bridge.

This bus is limited to 32-bit operation. This is because the upper address/data lines of PCI Bus 1.0 are multiplexed with the third Ethernet port on the MV64360 device.

CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) 81