Motorola CPCI-6115 manual 4.6 MV64360 Integrated 2 Megabit Sram, 4.8 MV64360 Watchdog Timer

MV64360 System Controller Functional Description

4.3.4.6MV64360 Integrated 2 Megabit SRAM

The MV64360 integrates 2 megabit (144-bit wide and 2 KB deep) of general purpose SRAM. It is accessible from the CPU or any of the other interfaces. It can be used as fast CPU access memory (6 cycles latency) and for off-loading DRAM traffic. A typical usage of the SRAM could be as a descriptor RAM for the Gigabit Ethernet port.

4.3.4.7MV64360 General-Purpose 32-bit Timer/Counters

There are four 32-bit timers/counters within the MV64360. Each timer/counter can be selected to operate as a timer or as a counter. The timing reference is based on the MV64360 Tclk input which is set at 133 MHz. Each counter/timer is capable of generating an interrupt. Refer to the MV64360 Data Sheet for additional information and programming details.

4.3.4.8MV64360 Watchdog Timer

The MV64360 internal watchdog timer is a 32-bit down counter that can be used to generate a non-maskable interrupt or reset the system in the event of unpredictable software behavior. After the watchdog timer is enabled, it becomes a free running counter that must be serviced periodically to keep it from expiring. Following reset, the watchdog timer is initially disabled but it is enabled during the MV64360 I2C device initialization. The watchdog timer has two output pins, WDNMI# and WDE#. The WDNMI# is asserted after the timer is enabled and the 24-bit NMI_VAL count is reached. The WDNMI# pin is connected to one of the MV64360 interrupt input pins so that an interrupt is generated when the NMI_VAL count is reached. The WDE# pin is asserted after the watchdog timer is enabled and the 32-bit watchdog count expires. The MV64360 holds WDE# asserted for the duration of 16 system cycles after reset assertion. The WDE# pin is connected to the board reset logic so that a board reset will be generated when WDE# is asserted. For additional details refer to the MV64360 Data Sheet.

4.3.4.9MV64360 I2O Message Unit

I2O compliant messaging for the CPCI-6115 board is provided by an I2O messaging unit integrated into the MV64360. The MV64360 messaging unit includes hardware hooks for message transfers between PCI devices and the CPU. This includes all of the registers required for implementing the I2O messaging, as defined in the Intelligent I/O (I2O) Standard specification. For additional details regarding the I2O messaging unit, refer to the MV64360 Data Sheet.

4.3.4.10 MV64360 Four-Channel Independent DMA Controller

The MV64360 incorporates four Independent DMA (IDMA) engines. Each IDMA engine has the capability to transfer data between any interface. Refer to the MV64360 Data Sheet for additional information and programming details.

4.3.4.11 MV64360 I2C Interface

A two-wire serial interface for the CPCI-6115 board is provided by a master/slave capable I2C serial controller integrated into the MV64360 device. The I2C serial controller provides two basic functions. The first function is to optionally provide MV64360 register initialization following a reset. The MV64360 can be configured (by jumper setting) to automatically read data out of a serial EEPROM following a reset and initialize any number of internal registers. In

CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D) 73