Motorola CPCI-6115 manual PCI1 DLL, PCI0 DLL, Mii/Gmii, Pcs

Functional DescriptionMV64360 System Controller

Table 4-3 MV64360 Power-Up Configuration Settings (continued)

		Default
Device AD	Select	Power-Up
Bus Signal	Option	Setting	Description	State of Bit vs. Function
AD[18]	Resistor	1	DRAM Clock	0	DRAM is running at a higher
			Select		frequency than the core clock
				1	DRAM is running at a same
					frequency as the core clock
AD[19]	Resistor	0	DRAM	0	DRAM address and control
			Address/Control		signals toggle on falling edge
			Delay		of DRAM clock
				1	DRAM address and control
					signals toggle on rising edge
					of DRAM clock
AD[21:20]	Resistors	11	DRAM control	00	Reserved
			path pipeline
				01	Reserved
			select
				10	Two pipe stages
				11	Three pipe stages
AD[24:22]	Resistors	000	DRAM read path	000	DRAM running in sync mode
			control	100
				001	DRAM running in async mode
				111
AD[25]	Fixed	0	Gigabit port2	0	Disable
			Enable	1	Enable
AD[28:26]	Resistors	000	PCI_1 DLL	000	DLL disable
			control
				001	Conventional PCI mode at
					66MHz
				101	PCI-X mode at 133 MHz
				110	PCI-X mode at 66 MHz
AD[31:29]	PLD	101	PCI_0 DLL	000	DLL disable
			control
				001	Conventional PCI mode at
					66MHz
				101	PCI-X mode at 133 MHz
				110	PCI-X mode at 66 MHz
TxD0[0]	Resistor	0	Gigabit port0	0	MII/GMII
			GMII/PCS Select
				1	PCS
TxD1[0]	Resistor	0	Gigabit port1	0	MII/GMII
			GMII/PCS Select
				1	PCS
TxD2[0]	Resistor	0	Gigabit port2	0	MII/GMII
			GMII/PCS Select
				1	PCS

78 CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)