Chapter 3 |
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| 30 | (D9) | DRQ0 | DMA Request 0 – Used by I/O resources to request DMA service. |
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| Must be held high until associated DACK0 line is active. |
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| 31 | (D10) | DACK5* | DMA Acknowledge 5 – Used by DMA controller to select the I/O |
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| resource requesting the bus, or to request ownership of the bus as a bus |
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| master device. Can also be used by the ISA bus master to gain control |
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| of the bus from the DMA controller. |
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| 32 | (D11) | DRQ5 | DMA Request 5 – Used by I/O resources to request DMA service. |
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| Must be held high until associated DACK5 line is active. |
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| 33 | (D12) | DACK6* | DMA Acknowledge 6 – Used by DMA controller to select the I/O |
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| resource requesting the bus, or to request ownership of the bus as a bus |
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| master device. Can also be used by the ISA bus master to gain control |
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| of the bus from the DMA controller. |
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| 34 | (D13) | DRQ6 | DMA Request 6 – Used by I/O resources to request DMA service. |
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| Must be held high until associated DACK6 line is active. |
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| 35 | (D14) | DACK7* | DMA Acknowledge 7 – Used by DMA controller to select the I/O |
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| resource requesting the bus, or to request ownership of the bus as a bus |
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| master device. Can also be used by the ISA bus master to gain control |
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| of the bus from the DMA controller. |
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| 36 | (D15) | DRQ7 | DMA Request 7 – Used by I/O resources to request DMA service. |
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| Must be held high until associated DACK7 line is active. |
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| 37 | (D16) | +5V | +5 volt power ±10% |
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| 38 | (D17) | MASTER* | Bus Master Assert – This signal is used by an ISA board along with a |
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| DRQ line to gain ownership of the ISA bus. Upon receiving a |
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| a device can pull |
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| system address, data, and control lines. After |
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| device should wait one CLK period before driving the address and data |
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| lines, and two clock periods before issuing a read or write command. |
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| 39 | (D18) | GND | Ground |
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| 40 | (D19) | GND | Ground |
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Notes: The shaded area denotes power or ground. The signals marked with * = Negative true logic.
32 | Reference Manual | ReadyBoard 700 |