2-4. Carriage Board
No. | Signal name | Function |
1,2 | A_GNDH | Head ground |
3 | HD2_C1 | Head data C1 |
4 | HD8_Y1 | Head data Y1 |
5 | VSS | Logic ground |
6 | PBK1 | Logic ground |
7,8 | B_GNDH | Head ground |
9 | HD3_SC1 | Head data SC1 |
10 | HD5_SM1 | Head data SM1 |
11 | HD4_M1 | Head data M1 |
12 | HENB1 | Head heat enable signal 1 |
13 | HD10_SM2 | Head data SM2 |
14 | VSS | Logic ground |
15 | HD11_M2 | Head data M2 |
16 | B_DiK | Logic ground |
17 | HD0_K1 | Head data BK1 |
18 | HENB0 | Head heat enable signal 0 |
19 | HENB3 | Head heat enable signal 3 |
20 | HLAT | Head data latch signal |
21 | HD12_SC2 | Head data SC2 |
22 | PBK2 | Logic ground |
23 | HD9_Y2 | Head data Y2 |
24 | HENB2 | Head heat enable signal 2 |
25 | HD1_K2 | Head data BK2 |
26 | A_DiK | Logic ground |
27,35 | HVDD | Head logic power supply +3.3V |
28 | ROM_CS | Head EEPROM chip select signal |
29 | HCLK | Head data transfer clock signal |
30 | ROM_DO | Head EEPROM data signal |
31 | HD13_C2 | Head data C2 |
32,40 | B_VH2 | Head drive power supply +24V |
33,34 | A_VH | Head logic power supply +24V |
36 | ROM_SK | Head EEPROM serial clock signal |
37 | ROM_DIO | Head EEPROM data signal |
38 | B_DiA | Diode senor anode |
39 | VHT | Head drive power supply +24V |
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<Part 3: 2. CONNECTOR LOCATION AND PIN LAYOUT; 
