Features | Cypress CY7C0430CV, CY7C0430BV instruction

CY7C0430BV

CY7C0430CV

10 Gb/s 3.3V QuadPort™ DSE Family

Features

•QuadPort™ datapath switching element (DSE) family allows four independent ports of access for data path management and switching

•High-bandwidth data throughput up to 10 Gb/s

•133-MHz[1]port speed x 18-bit-wide interface × 4 ports

•High-speed clock to data access 4.2 ns (max.)

•Synchronous pipelined device

— 1-Mb (64K × 18) switch array

•0.25-micron CMOS for optimum speed/power

•IEEE 1149.1 JTAG boundary scan

•Width and depth expansion capabilities

•BIST (Built-In Self-Test) controller

•Dual Chip Enables on all ports for easy depth expansion

•Separate upper-byte and lower-byte controls on all ports

•Simple array partitioning

—Internal mask register controls counter wrap-around

—Counter-Interrupt flags to indicate wrap-around

—Counter and mask registers readback on address

•272-ball BGA package (27-mm × 27-mm × 1.27-mm ball pitch)

•Commercial and industrial temperature ranges

•3.3V low operating power

—Active = 750 mA (maximum)

—Standby = 15 mA (maximum

QuadPort DSE Family Applications

PORT 1

PORT 2

PORT 1

PORT 3

PORT 4

BUFFERED SWITCH

PORT 2

PORT 3

PORT 4

REDUNDANT DATA MIRROR

Note:

1. fMAX2 for commercial is 135 MHz and for industrial is 133 MHz.

Cypress Semiconductor Corporation	•	198 Champion Court • San Jose, CA 95134-1709	•	408-943-2600
Document #: 38-06027 Rev. *B		Revised May 23, 2006

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Cypress CY7C0430CV, CY7C0430BV manual Features, QuadPort DSE Family Applications, Cypress Semiconductor Corporation

Contents

QuadPort DSE Family Applications FeaturesCypress Semiconductor Corporation Processor Pre-processed Data Path Functional DescriptionProcessor Processed Data Path Queue #1 Port 1 Operation-control Logic Blocks2 Top Level Logic Block Diagram Address Readback is independent of CEs Port 1 Operation-Control Logic Block Diagram Ball Grid Array BGA Top View Pin Configuration Pin Definitions Selection GuideCY7C0430CV Unit Port Description Counter Interrupt Flag Output . Flag is asserted LOW Mask Register Readback Input . When asserted LOW Maximum Ratings Electrical Characteristics Over the Operating RangeOperating Range Capacitance AC Test Load Three-State DelayNormal Load TAP Load Chip Enable Hold Time Chip Enable Set-up TimeOutput Enable to Data Valid Maximum Frequency Jtag Timing and Switching Waveforms Master Reset10 Switching Waveforms Address CLKData OUT Latency Read-to-Write-to-Read OE = Bank Select Read 17Address B1 Read No Operation Write Read with Address Counter Advance23 Read-to-Write-to-Read OE Controlled19, 20, 21Cntld Cntinc Dataout Address Internal Write with Address Counter Advance 24Write External Write with Counter Hold Counter Write Read Reset Address Counter Reset 21, 26Data Data OUT Address n Cntrd Internal Load and Read Address Counter28Load Read Data with Counter External Address Internal Mkld Load and Read Mask RegisterMkrd Mask Internal Value Load Read Mask Register Value Port 1 Write to Port 2 Read34, 35 Mailbox Interrupt Timing40, 41, 42, 43 Counter Interrupt 37, 38 Operation Mode Operation Interrupts Master ResetInterrupt Operation Example Port Function Cntrd Mkrd Address Counter Control OperationsCntinc = Cntld = Cntrst = CLK Counter-Mask Register Test Access Port TAP-Test Clock TCK Disabling the Jtag FeatureTest Mode Select Performing a TAP Reset Identification ID Register Non-Debug Mode Go-NoGoTAP Instruction Set Mbist Control States Debug ModeBoundary Scan Cells BSC P4IO17-9 EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State Diagram FSM53 MUX JTAG/BIST TAP Controller Block DiagramMbist Debug Register MDR 391 Bist TAP Controller Instruction Identification Codes Description Scan Registers Sizes Register Name Bit SizePlaces the bypass register BYR between TDI and TDO Between TDI and TDO Mbist Control Register MCR MCR10 Mode CE0 Boundary Scan Order Cell # Signal Name Bump Ball IDCLKP4 CLKP3 CLKP2 Ordering Information Lead Pbga 27 x 27 x 2.33 mm BG272 Package Diagram Document History Issue Orig. Description of Change DateSZV FSG