CY7C0430BV
CY7C0430CV
Document #: 38-06027 Rev. *B Page 14 of 37
Bank Select Read[17, 18]
Read-to-Write-to-Read (OE = VIL)[19, 20, 21, 22]Notes:
17.In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each bank consists of one QuadPort DSE device from this data sheet.
ADDRESS(B1) = ADDRESS(B2).
18.LB = UB = OE = CNTLD = VIL; MRST = CNTRST= MKLD = VIH.
19.Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
20.LB = UB = CNTLD = VIL; MRST = CNTRST = MKLD = VIH.
21.Addresses do not have to be accessed sequentially since CNTLD = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference only.
22.During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
Switching Waveforms (continued)
Q3
Q1
Q0
Q2
A0A1A2A3A4A5
Q4
A0A1A2A3A4A5
tSA tHA
tSC tHC
tSA tHA
tSC tHC
tSC tHC
tSC tHC tCKHZ
tDC
tDC
tCD2
tCKLZ
tCD2 tCD2 tCKHZ
tCKLZ
tCD2 tCKHZ
tCKLZ
tCD2
tCH2 tCL2
tCYC2
CLK
ADDRESS(B1)
CE(B1)
DATAOUT(B2)
DATAOUT(B1)
ADDRESS(B2)
CE(B2)
tCYC2tCL2
tCH2
tHC
tSC
tHW
tSW
tHA
tSA
tHW
tSW
tCD2 tCKHZ
tSD tHD
tCKLZ
tCD2
No Operation WriteRead Read
CLK
CE
R/W
ADDRESS
DATAIN
DATAOUT
AnAn+1 An+2 An+2
Dn+2
An+3 An+4
QnQn+3
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