Scan Registers Sizes Register Name Bit Size | Cypress CY7C0430CV

CY7C0430BV

CY7C0430CV

Table 5. Scan Registers Sizes

Register Name	Bit Size

Instruction (IR)	4

Bypass (BYR)	1

Identification (IDR)	32

MBIST Control (MCR)	2

MBIST Result (MRR)	25

MBIST Debug (MDR)	100

Boundary Scan (BSR)	392

Table 6. Instruction Identification Codes

	Instruction		Code		Description

	EXTEST	0000		Captures the Input/Output ring contents. Places the boundary scan register (BSR)
				between the TDI and TDO.
	BYPASS	1111		Places the bypass register (BYR) between TDI and TDO.

	IDCODE	0111		Loads the ID register (IDR) with the vendor ID code and places the register
				between TDI and TDO.
	HIGHZ	0110		Places the BYR between TDI and TDO. Forces all QuadPort DSE device output
				drivers to a High-Z state.
	CLAMP	0101		Controls boundary to 1/0. Uses BYR.

	SAMPLE/PRELOAD	0001		Captures the Input/Output ring contents. Places the boundary scan register (BSR)
				between TDI and TDO.
	CYBIST	1000		Invokes MBIST. Places the MBIST Debug register (MDR) between TDI and TDO.

	INT_SCAN	0010		Scans out pass-fail information. Places MBIST Result Register (MRR) between TDI
				and TDO.
	MCR_SCAN	0011		Presets CYBIST mode. Places MBIST Control Register (MCR) between TDI and TDO.

	RESERVED		All other codes	Seven combinations are reserved. Do not use other than the above.

	Table 7. MBIST Control States

	States Code		State Name		Description

	000001		movi_zeros		Port 1 write all zeros to the QuadPort DSE device memory using Moving
					Inversion Algorithm (MIA).
	000011		movi_1_upcnt		Up count from 0 to 64K (depth of QuadPort DSE device). All ports read 0s, then
					Port 1 writes 1s to all memory locations using MIA, then all ports read 1s. MIA
					read0_write1_read1 (MIA_r0w1r1).
	000010		movi_0_upcnt		Up count from 0 to 64K. All ports read 1s, then Port 1 writes 0s, then all ports
					read 0s (MIA_r1w0r0).
	000110		movi_1_downcnt		Down count from 64K to 0. MIA_r0w1r1.

	000111		movi_0_downcnt		Down count MIA_r1w0r0.

	000101		movi_read		Read all 0s.


	000100		mar2_zeros		Port 1 write all zeros to memory using March2 Algorithm (M2A).

	001100		mar2_1_upcnt		Up count M2A_r0w1r1.

	001101		mar2_0_upcnt		Up count M2A_r1w0r0.

	001111		mar2_1_downcnt		Down count M2A_r0w1r1.

	001110		mar2_0_downcnt		Down count M2A_r1w0r0.

	001010		mar2_read		Read all 0s.


	001011		chkr_w		Port 1 writes topological checkerboard data to memory.

Document #: 38-06027 Rev. *B					Page 31 of 37

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Cypress CY7C0430CV, CY7C0430BV Scan Registers Sizes Register Name Bit Size, Instruction Identification Codes Description

Contents

QuadPort DSE Family Applications FeaturesCypress Semiconductor Corporation Queue #1 Functional DescriptionProcessor Pre-processed Data Path Processor Processed Data Path Port 1 Operation-control Logic Blocks2 Top Level Logic Block Diagram Address Readback is independent of CEs Port 1 Operation-Control Logic Block Diagram Ball Grid Array BGA Top View Pin Configuration Port Description Selection GuidePin Definitions CY7C0430CV Unit Counter Interrupt Flag Output . Flag is asserted LOW Mask Register Readback Input . When asserted LOW Capacitance Electrical Characteristics Over the Operating RangeMaximum Ratings Operating Range TAP Load Three-State DelayAC Test Load Normal Load Maximum Frequency Chip Enable Set-up TimeChip Enable Hold Time Output Enable to Data Valid Jtag Timing and Switching Waveforms Master Reset10 Switching Waveforms Latency CLKAddress Data OUT Read No Operation Write Bank Select Read 17Read-to-Write-to-Read OE = Address B1 Dataout Read-to-Write-to-Read OE Controlled19, 20, 21Read with Address Counter Advance23 Cntld Cntinc Counter Hold Write with Address Counter Advance 24Address Internal Write External Write with Address n Counter Reset 21, 26Counter Write Read Reset Address Data Data OUT Cntrd Internal Load and Read Address Counter28Load Read Data with Counter External Address Internal Load Read Mask Register Value Load and Read Mask RegisterMkld Mkrd Mask Internal Value Port 1 Write to Port 2 Read34, 35 Mailbox Interrupt Timing40, 41, 42, 43 Counter Interrupt 37, 38 Operation Mode Operation Port Function Master ResetInterrupts Interrupt Operation Example Cntrd Mkrd Address Counter Control OperationsCntinc = Cntld = Cntrst = CLK Counter-Mask Register Performing a TAP Reset Disabling the Jtag FeatureTest Access Port TAP-Test Clock TCK Test Mode Select Identification ID Register Non-Debug Mode Go-NoGoTAP Instruction Set P4IO17-9 Debug ModeMbist Control States Boundary Scan Cells BSC EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State Diagram FSM53 Bist TAP Controller JTAG/BIST TAP Controller Block DiagramMUX Mbist Debug Register MDR 391 Between TDI and TDO Scan Registers Sizes Register Name Bit SizeInstruction Identification Codes Description Places the bypass register BYR between TDI and TDO Mbist Control Register MCR MCR10 Mode CLKP3 Boundary Scan Order Cell # Signal Name Bump Ball IDCE0 CLKP4 CLKP2 Ordering Information Lead Pbga 27 x 27 x 2.33 mm BG272 Package Diagram FSG Issue Orig. Description of Change DateDocument History SZV