Ordering Information | Cypress CY7C0430CV, CY7C0430BV manual

CY7C0430BV

CY7C0430CV

Table 9. Boundary Scan Order (continued)

Cell #	Signal Name	Bump (Ball) ID

330	IO13_P2	A4

332	IO14_P2	B4

334	IO15_P2	A3

336	IO16_P2	B3

338	IO17_P2	A2

340	IO9_P1	C9

342	IO10_P1	A10

344	IO11_P1	B9

346	IO12_P1	A9

348	IO13_P1	B8

350	IO14_P1	A8

352	IO15_P1	C6

354	IO16_P1	A7

356	IO17_P1	B7

358	IO9_P3	A15

360	IO10_P3	B15

362	IO11_P3	A16

364	IO12_P3	B16

366	IO13_P3	A17

368	IO14_P3	B17

370	IO15_P3	A18

372	IO16_P3	B18

374	IO17_P3	A19

376	IO9_P4	C12

378	IO10_P4	A11

380	IO11_P4	B12

382	IO12_P4	A12

384	IO13_P4	B13

386	IO14_P4	A13

388	IO15_P4	C15

390	IO16_P4	A14

392	IO17_P4	B14

Ordering Information

10 Gb/s 3.3V QuadPort DSE Family 1 Mb (64K × 18)

	Speed	Ordering Code	Package	Package Type	Operating
	(MHz)	Ordering Code	Name	Package Type	Range

	133	CY7C0430BV-133BGI	BG272	272-ball Grid Array (BGA)	Industrial

		CY7C0430CV-133BGI	BG272	272-ball Grid Array (BGA)	Industrial

	100	CY7C0430BV-100BGC	BG272	272-ball Grid Array (BGA)	Commercial

		CY7C0430BV-100BGI	BG272	272-ball Grid Array (BGA)	Industrial

Document #: 38-06027 Rev. *B					Page 35 of 37

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Cypress CY7C0430CV, CY7C0430BV manual Ordering Information

Contents

Cypress Semiconductor Corporation FeaturesQuadPort DSE Family Applications Queue #1 Functional DescriptionProcessor Pre-processed Data Path Processor Processed Data Path Port 1 Operation-control Logic Blocks2 Top Level Logic Block Diagram Address Readback is independent of CEs Port 1 Operation-Control Logic Block Diagram Ball Grid Array BGA Top View Pin Configuration Port Description Selection GuidePin Definitions CY7C0430CV Unit Counter Interrupt Flag Output . Flag is asserted LOW Mask Register Readback Input . When asserted LOW Capacitance Electrical Characteristics Over the Operating RangeMaximum Ratings Operating Range TAP Load Three-State DelayAC Test Load Normal Load Maximum Frequency Chip Enable Set-up TimeChip Enable Hold Time Output Enable to Data Valid Jtag Timing and Switching Waveforms Master Reset10 Switching Waveforms Latency CLKAddress Data OUT Read No Operation Write Bank Select Read 17Read-to-Write-to-Read OE = Address B1 Dataout Read-to-Write-to-Read OE Controlled19, 20, 21Read with Address Counter Advance23 Cntld Cntinc Counter Hold Write with Address Counter Advance 24Address Internal Write External Write with Address n Counter Reset 21, 26Counter Write Read Reset Address Data Data OUT Load Read Data with Counter External Address Internal Load and Read Address Counter28Cntrd Internal Load Read Mask Register Value Load and Read Mask RegisterMkld Mkrd Mask Internal Value Port 1 Write to Port 2 Read34, 35 Mailbox Interrupt Timing40, 41, 42, 43 Counter Interrupt 37, 38 Operation Mode Operation Port Function Master ResetInterrupts Interrupt Operation Example Cntinc = Cntld = Cntrst = CLK Address Counter Control OperationsCntrd Mkrd Counter-Mask Register Performing a TAP Reset Disabling the Jtag FeatureTest Access Port TAP-Test Clock TCK Test Mode Select TAP Instruction Set Non-Debug Mode Go-NoGoIdentification ID Register P4IO17-9 Debug ModeMbist Control States Boundary Scan Cells BSC EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State Diagram FSM53 Bist TAP Controller JTAG/BIST TAP Controller Block DiagramMUX Mbist Debug Register MDR 391 Between TDI and TDO Scan Registers Sizes Register Name Bit SizeInstruction Identification Codes Description Places the bypass register BYR between TDI and TDO Mbist Control Register MCR MCR10 Mode CLKP3 Boundary Scan Order Cell # Signal Name Bump Ball IDCE0 CLKP4 CLKP2 Ordering Information Lead Pbga 27 x 27 x 2.33 mm BG272 Package Diagram FSG Issue Orig. Description of Change DateDocument History SZV