Counter Interrupt 37, 38 | Cypress CY7C0430CV, CY7C0430BV instruction

						CY7C0430BV
						CY7C0430CV
Switching Waveforms (continued)
Counter Interrupt [37, 38, 39]
		tCYC2
	tCH2	tCL2
CLK
EXTERNAL	007Fh	xx7Dh
ADDRESS
tSMLD		tHMLD
MKLD
CNTLD		tSCLD	tHCLD
CNTLD
CNTINC			tSCINC	tHCINC
CNTINC
COUNTER
INTERNAL		An	xx7Dh	xx7Eh	xx7Fh	xx00h	xx00h
ADDRESS		An	xx7Dh	xx7Eh	xx7Fh	xx00h	xx00h
ADDRESS
CNTINT					tSCINT		tRCINT
CNTINT
Mailbox Interrupt Timing[40, 41, 42, 43, 44]
	tCYC2
	tCH2	tCL2

CLKP1

tSA tHA

PORT-1

FFFE

An

An+1

An+2

An+3

ADDRESS

tSINT

tRINT

INT

P2

tCYC2

CLKP2

tCH2

tCL2

tSA

tHA

PORT-2	Am
ADDRESS

Am+1

FFFE

Am+3

Am+4

Notes:

37.CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = CNTRD = MKRD = VIH.

38.CNTINT is always driven.

39.CNTINC goes LOW as the counter address masked portion is incremented from xx7Fh to xx00h. The “x” is “Don’t Care.”

40.CE0 = OE = LB = UB = CNTLD =VIL; CE1 = CNTRST = MRST = CNTRD = CNTINC = MKRD = MKLD =VIH.

41.Address “FFFE” is the mailbox location for Port 2.

42.Port 1 is configured for Write operation, and Port 2 is configured for Read operation.

43.Port 1 and Port 2 are used for simplicity. All four ports can write to or read from any mailbox.

44.Interrupt flag is set with respect to the rising edge of the write clock, and is reset with respect to the rising edge of the read clock.

Document #: 38-06027 Rev. *B

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Cypress CY7C0430CV, CY7C0430BV manual Counter Interrupt 37, 38, Mailbox Interrupt Timing40, 41, 42, 43

Contents

Features QuadPort DSE Family ApplicationsCypress Semiconductor Corporation Processor Pre-processed Data Path Functional DescriptionProcessor Processed Data Path Queue #1 Port 1 Operation-control Logic Blocks2 Top Level Logic Block Diagram Address Readback is independent of CEs Port 1 Operation-Control Logic Block Diagram Ball Grid Array BGA Top View Pin Configuration Pin Definitions Selection GuideCY7C0430CV Unit Port Description Counter Interrupt Flag Output . Flag is asserted LOW Mask Register Readback Input . When asserted LOW Maximum Ratings Electrical Characteristics Over the Operating RangeOperating Range Capacitance AC Test Load Three-State DelayNormal Load TAP Load Chip Enable Hold Time Chip Enable Set-up TimeOutput Enable to Data Valid Maximum Frequency Jtag Timing and Switching Waveforms Master Reset10 Switching Waveforms Address CLKData OUT Latency Read-to-Write-to-Read OE = Bank Select Read 17Address B1 Read No Operation Write Read with Address Counter Advance23 Read-to-Write-to-Read OE Controlled19, 20, 21Cntld Cntinc Dataout Address Internal Write with Address Counter Advance 24Write External Write with Counter Hold Counter Write Read Reset Address Counter Reset 21, 26Data Data OUT Address n Load and Read Address Counter28 Cntrd InternalLoad Read Data with Counter External Address Internal Mkld Load and Read Mask RegisterMkrd Mask Internal Value Load Read Mask Register Value Port 1 Write to Port 2 Read34, 35 Mailbox Interrupt Timing40, 41, 42, 43 Counter Interrupt 37, 38 Operation Mode Operation Interrupts Master ResetInterrupt Operation Example Port Function Address Counter Control Operations Cntrd MkrdCntinc = Cntld = Cntrst = CLK Counter-Mask Register Test Access Port TAP-Test Clock TCK Disabling the Jtag FeatureTest Mode Select Performing a TAP Reset Non-Debug Mode Go-NoGo Identification ID RegisterTAP Instruction Set Mbist Control States Debug ModeBoundary Scan Cells BSC P4IO17-9 EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State Diagram FSM53 MUX JTAG/BIST TAP Controller Block DiagramMbist Debug Register MDR 391 Bist TAP Controller Instruction Identification Codes Description Scan Registers Sizes Register Name Bit SizePlaces the bypass register BYR between TDI and TDO Between TDI and TDO Mbist Control Register MCR MCR10 Mode CE0 Boundary Scan Order Cell # Signal Name Bump Ball IDCLKP4 CLKP3 CLKP2 Ordering Information Lead Pbga 27 x 27 x 2.33 mm BG272 Package Diagram Document History Issue Orig. Description of Change DateSZV FSG