Cypress CY7C0430BV, CY7C0430CV Counter Interrupt , Mailbox Interrupt Timing

CY7C0430BV
CY7C0430CV
Document #: 38-06027 Rev. *B Page 21 of 37
Counter Interrupt [37, 38, 39]
Mailbox Interrupt Timing[40, 41, 42, 43, 44]
Notes:
37.CE0 = OE = LB = UB = VIL; CE1 = R/W = CNTRST = MRST = CNTRD = MKRD = VIH.
38.CNTINT is always driven.
39.CNTINC goes LOW as the counter address masked portion is incremented from xx7Fh to xx00h. The “x” is “Don’t Care.”
40.CE0 = OE = LB = UB = CNTLD =VIL; CE1 = CNTRST = MRST = CNTRD = CNTINC = MKRD = MKLD =VIH.
41.Address “FFFE” is the mailbox location for Port 2.
42.Port 1 is configured for Write operation, and Port 2 is configured for Read operation.
43.Port 1 and Port 2 are used for simplicity. All four ports can write to or read from any mailbox.
44.Interrupt flag is set with respect to the rising edge of the write clock, and is reset with respect to the rising edge of the read clock.
Switching Waveforms (continued)
tSMLD tHMLD
tSCLD tHCLD
tCH2 tCL2
tCYC2
CLK
MKLD
CNTLD
Anxx7Eh
INTERNAL
ADDRESS xx7Fh xx00h
xx7Dh
EXTERNAL
ADDRESS
tSCINC tHCINC
CNTINC
COUNTER
007Fh
xx7Dh xx00h
CNTINT
tSCINT tRCINT
t
CH2
t
CL2
t
CYC2
CLK
P1
tCH2 tCL2
tCYC2
CLKP2
FFFE
tSA tHA
An+3
AnAn+1 An+2
PORT-1
ADDRESS
AmAm+4
Am+1 FFFE Am+3
PORT-2
ADDRESS
INTP2
tSA tHA
tSINT
tRINT
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