Mode Operation | Cypress CY7C0430BV, CY7C0430CV specification

CY7C0430BV

CY7C0430CV

Table 1. Read/Write and Enable Operation (Any Port)[45, 46, 47]

Inputs

Outputs

OE

CLK

CE

0

CE1

R/W

I/O0–I/O17

Operation

X

H

X

X

High-Z

Deselected

X

X

L

X

High-Z

Deselected

X

L

H

L

DIN

Write

L

L

H

H

DOUT

Read

H

X

L

H

X

High-Z

Outputs Disabled

Table 2. Address Counter and Counter-Mask Register Control Operation (Any Port)[45, 48, 49]

CLK

MRST

CNTRST

MKLD

CNTLD

CNTINC

CNTRD

MKRD

Mode

Operation

X

L

X

X

X

X

X

X

Master-

Counter/Address Register Reset and Mask

Reset

Register Set (resets entire chip as per reset

state table)

H

L

X

X

X

X

X

Reset

Counter/Address Register Reset

H

H

L

X

X

X

X

Load

Load of Address Lines into Mask Register

H

H

H

L

X

X

X

Load

Load of Address Lines into Counter/Address

Register

H

H

H

H

L

X

X

Increment

Counter Increment

H

H

H

H

H

L

X

Readback

Readback Counter on Address Lines

H

H

H

H

H

H

L

Readback

Readback Mask Register on Address Lines

H

H

H

H

H

H

H

Hold

Counter Hold

Notes:

45.“X” = “Don’t Care,” “H” = VIH, “L” = VIL.

46.OE is an asynchronous input signal.

47.When CE changes state, deselection and read happen after one cycle of latency.

48.CE0 = OE = VIL; CE1 = R/W = VIH.

49.Counter operation and mask register operation are independent of Chip Enables.

Document #: 38-06027 Rev. *B

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Cypress CY7C0430BV, CY7C0430CV manual Mode Operation

Contents

QuadPort DSE Family Applications FeaturesCypress Semiconductor Corporation Processor Processed Data Path Functional DescriptionProcessor Pre-processed Data Path Queue #1 Top Level Logic Block Diagram Port 1 Operation-control Logic Blocks2 Port 1 Operation-Control Logic Block Diagram Address Readback is independent of CEs Pin Configuration Ball Grid Array BGA Top View CY7C0430CV Unit Selection GuidePin Definitions Port Description Mask Register Readback Input . When asserted LOW Counter Interrupt Flag Output . Flag is asserted LOW Operating Range Electrical Characteristics Over the Operating RangeMaximum Ratings Capacitance Normal Load Three-State DelayAC Test Load TAP Load Output Enable to Data Valid Chip Enable Set-up TimeChip Enable Hold Time Maximum Frequency Jtag Timing and Switching Waveforms Switching Waveforms Master Reset10 Data OUT CLKAddress Latency Address B1 Bank Select Read 17Read-to-Write-to-Read OE = Read No Operation Write Cntld Cntinc Read-to-Write-to-Read OE Controlled19, 20, 21Read with Address Counter Advance23 Dataout Write External Write with Write with Address Counter Advance 24Address Internal Counter Hold Data Data OUT Counter Reset 21, 26Counter Write Read Reset Address Address n Cntrd Internal Load and Read Address Counter28Load Read Data with Counter External Address Internal Mkrd Mask Internal Value Load and Read Mask RegisterMkld Load Read Mask Register Value Port 1 Write to Port 2 Read34, 35 Counter Interrupt 37, 38 Mailbox Interrupt Timing40, 41, 42, 43 Mode Operation Operation Interrupt Operation Example Master ResetInterrupts Port Function Cntrd Mkrd Address Counter Control OperationsCntinc = Cntld = Cntrst = CLK Counter-Mask Register Test Mode Select Disabling the Jtag FeatureTest Access Port TAP-Test Clock TCK Performing a TAP Reset Identification ID Register Non-Debug Mode Go-NoGoTAP Instruction Set Boundary Scan Cells BSC Debug ModeMbist Control States P4IO17-9 TAP Controller State Diagram FSM53 EXIT2-IR UPDATE-DR UPDATE-IR Mbist Debug Register MDR 391 JTAG/BIST TAP Controller Block DiagramMUX Bist TAP Controller Places the bypass register BYR between TDI and TDO Scan Registers Sizes Register Name Bit SizeInstruction Identification Codes Description Between TDI and TDO Mbist Control Register MCR MCR10 Mode CLKP4 Boundary Scan Order Cell # Signal Name Bump Ball IDCE0 CLKP3 CLKP2 Ordering Information Package Diagram Lead Pbga 27 x 27 x 2.33 mm BG272 SZV Issue Orig. Description of Change DateDocument History FSG