Cypress CY7C0430BV, CY7C0430CV CY7C0430BV CY7C0430CV

CY7C0430BVCY7C0430CV

Document #: 38-06027 Rev. *B Page 30 of 37

JTAG/BIST TAP Controller Block Diagram

Table 4. Identification Register Definitions

Instruction Field Value Description

Revision Number (31:28) 1h Reserved for version number

Cypress Device ID (27:12) C000h Defines Cypress part number

Cypress JEDEC ID (11:1) 34h Allows unique identification of QuadPort DSE device vendor

ID Register Presence (0) 1Indicate the presence of an ID register

3 2 1 0

24 23 0

31 30 29 0

99 0

0391

Bypass Register (BYR)

Instruction Register (IR)

Identification Register (IDR)

Boundary Scan Register (BSR)

MBIST Result Register (MRR)

MBIST Debug Register (MDR)

TDI Selection

Circuitry TDO

TCK

TMS

TAP

CONTROLLER

BIST

CONTROLLER

MRST

MEMORY

CELL

CLKBIST

MBIST Control Register (MCR)

(MUX)

1 0

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Contents

Main 10 Gb/s 3.3V QuadPort DSE Family Features QuadPort DSE Family Applications Functional Description CY7C0430BV CY7C0430CV Top Level Logic Block Diagram CY7C0430BV CY7C0430CV Port 1 Operation-Control Logic Block Diagram Pin Configuration 272-ball Grid Array (BGA) Top Vi ew Note: 4. Central Leads are for thermal dissipation only. They are connected to device VSS. 1234567891011121314151617181920 A B Selection Guide Pin Definitions CY7C0430BV CY7C0430CV Pin Definitions Maximum Ratings Operating Range Electrical Characteristics JTAG TAP Electrical Characteristics Capacitance AC Test Load (a) Normal Load (c) TAP Load (b) Three-State Delay All Input Pulses Switching Characteristics JTAG Timing and Switching Waveforms Switching Characteristics Switching Waveforms Read Cycle Bank Select Read Read-to-Write-to-Read (OE = VIL)[19, 20, 21, 22] Read-to-Write-to-Read (OE Controlled)[19, 20, 21, 22] Read with Address Counter Advance Write with Address Counter Advance Counter Reset Load and Read Address Counter Note 29 Note 30 Load and Read Mask Register Note 29 Note 30 Port 1 Write to Port 2 Read PORT-1 PORT-2 Counter Interrupt Mailbox Interrupt Timing Page Master Reset Interrupts Address Counter Control Operations Counter/ Address Register Counter-Mask Register IEEE 1149.1 Serial Boundary Scan (JTAG) and Memory Built-In-Self-Test (MBIST) Page Page Page CY7C0430BV CY7C0430CV JTAG/BIST TAP Controller Block Diagram Page Page Page Page Ordering Information Package Diagram Document History Page