Cypress CY7C0430CV, CY7C0430BV manual Mask Register Readback Input . When asserted LOW

CY7C0430BV

CY7C0430CV

Pin Definitions (continued)

Port 1

Port 2

Port 3

Port 4

Description

P1

P2

P3

P4

Counter Readback Input. When asserted LOW, the

CNTRD

CNTRD

CNTRD

CNTRD

internal address value of the counter will be read back on

the address lines. During CNTRD operation, both CNTLD

and CNTINC must be HIGH. Counter readback operation

has higher priority over mask register readback operation.

Counter readback operation is independent of port chip

enables. If address readback operation occurs with chip

enables active (CE0 = LOW, CE1 = HIGH), the data lines

(I/Os) will be three-stated. The readback timing will be

valid after one no-operation cycle plus tCD2 from the rising

edge of the next cycle.

P1

P2

P3

P4

Mask Register Readback Input. When asserted LOW,

MKRD

MKRD

MKRD

MKRD

the value of the mask register will be readback on address

lines. During mask register readback operation, all

counter and MKLD inputs must be HIGH (see Counter

and Mask Register Operations truth table). Mask register

readback operation is independent of port chip enables.

If address readback operation occurs with chip enables

active (CE0 = LOW, CE1 = HIGH), the data lines (I/Os) will

be three-stated. The readback will be valid after one

no-operation cycle plus tCD2 from the rising edge of the

next cycle.

P1

P2

P3

P4

Counter Interrupt Flag Output. Flag is asserted LOW

CNTINT

CNTINT

CNTINT

CNTINT

for one clock cycle when the counter wraps around to

location zero.

Interrupt Flag Output. Interrupt permits communications

INTP1

INTP2

INTP3

INTP4

between all four ports. The upper four memory locations

can be used for message passing. Example of operation:

INTP4 is asserted LOW when another port writes to the

mailbox location of Port 4. Flag is cleared when Port 4

reads the contents of its mailbox. The same operation is

applicable to ports 1, 2, and 3.

TMS

JTAG Test Mode Select Input. It controls the advance of

JTAG TAP state machine. State machine transitions occur

on the rising edge of TCK.

TCK

JTAG Test Clock Input. This can be CLK of any port or

an external clock connected to the JTAG TAP.

TDI

JTAG Test Data Input. This is the only data input. TDI

inputs will shift data serially in to the selected register.

TDO

JTAG Test Data Output. This is the only data output.

TDO transitions occur on the falling edge of TCK. TDO

normally three-stated except when captured data is

shifted out of the JTAG TAP.

CLKBIST

BIST Clock Input.

GND

Thermal Ground for Heat Dissipation.

VSS

Ground Input.

VDD

Power Input.

VSS1

Address Lines Ground Input.

VDD1

Address Lines Power Input.

VSS2

Data Lines Ground Input.

VDD2

Data Lines Power Input.

Document #: 38-06027 Rev. *B Page 7 of 37

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