Cypress CY7C0430BV, CY7C0430CV CY7C0430BV CY7C0430CV

CY7C0430BVCY7C0430CV

Document #: 38-06027 Rev. *B Page 4 of 37

Addr.

Read

Port 1 Operation-Control Logic Block Diagram

R/WP1

CE0P1

CE1P1

LBP1

OEP1

UBP1

I/O9P1–I/O17P1

I/O0P1–I/O8P1

I/O

Control

Counter/

A0P1–A15P1

CLKP1

CNTLDP1

CNTINCP1

CNTRSTP1

MKLDP1

CNTINTP1

MKRDP1

Mask Register

Port-1

Port 1

64K× 18

QuadPort

DSE Array

Port 1

Port 2

Port 4

Port 3

Address

Readback

Port 1

CNTRDP1

Port 1

Address

Decode

Port 1

Interrupt

Logic

R/WP1

CE0P1

CE1P1

OEP1

INTP1

CLKP1

MRST

Priority

Decision

Logic

MRST

(Address Readback is independent of CEs)

LBP1

UBP1

[+] Feedback

Contents

Main 10 Gb/s 3.3V QuadPort DSE Family Features QuadPort DSE Family Applications Functional Description CY7C0430BV CY7C0430CV Top Level Logic Block Diagram CY7C0430BV CY7C0430CV Port 1 Operation-Control Logic Block Diagram Pin Configuration 272-ball Grid Array (BGA) Top Vi ew Note: 4. Central Leads are for thermal dissipation only. They are connected to device VSS. 1234567891011121314151617181920 A B Selection Guide Pin Definitions CY7C0430BV CY7C0430CV Pin Definitions Maximum Ratings Operating Range Electrical Characteristics JTAG TAP Electrical Characteristics Capacitance AC Test Load (a) Normal Load (c) TAP Load (b) Three-State Delay All Input Pulses Switching Characteristics JTAG Timing and Switching Waveforms Switching Characteristics Switching Waveforms Read Cycle Bank Select Read Read-to-Write-to-Read (OE = VIL)[19, 20, 21, 22] Read-to-Write-to-Read (OE Controlled)[19, 20, 21, 22] Read with Address Counter Advance Write with Address Counter Advance Counter Reset Load and Read Address Counter Note 29 Note 30 Load and Read Mask Register Note 29 Note 30 Port 1 Write to Port 2 Read PORT-1 PORT-2 Counter Interrupt Mailbox Interrupt Timing Page Master Reset Interrupts Address Counter Control Operations Counter/ Address Register Counter-Mask Register IEEE 1149.1 Serial Boundary Scan (JTAG) and Memory Built-In-Self-Test (MBIST) Page Page Page CY7C0430BV CY7C0430CV JTAG/BIST TAP Controller Block Diagram Page Page Page Page Ordering Information Package Diagram Document History Page