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CY7C0430BV
CY7C0430CV
Master Reset
The QuadPort DSE device undergoes a complete reset by taking its Master Reset (MRST) input LOW. The Master Reset input can switch asynchronously to the clocks. A Master Reset initializes the internal burst counters to zero, and the counter mask registers to all ones (completely unmasked). A Master Reset also forces the Mailbox Interrupt (INT) flags and the Counter Interrupt (CNTINT) flags HIGH, resets the BIST controller, and takes all registered control signals to a deselected read state.[50] A Master Reset must be performed on the QuadPort DSE device after
Interrupts
The upper four memory locations may be used for message passing and permit communications between ports. Table 3 shows the interrupt operation for all ports. For the
Table 3. Interrupt Operation Example
the mailbox for Port 1, FFFE is the mailbox for Port 2, FFFD is the mailbox for Port 3, and FFFC is the mailbox for Port 4. Table 3 shows that in order to set Port 1 INTP1 flag, a write by any other port to address FFFF will assert INTP1 LOW. A read of FFFF location by Port 1 will reset INTP1 HIGH. When one port writes to the other port’s mailbox, the Interrupt flag (INT) of the port that the mailbox belongs to is asserted LOW. The Interrupt is reset when the owner (port) of the mailbox reads the contents of the mailbox. The interrupt flag is set in a
Each port can read the other port’s mailbox without resetting the interrupt. If an application does not require message passing, INT pins should be treated as
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| Port 2 |
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| Port 3 |
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| Port 4 |
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Function |
| INT | P1 |
| INT | P2 |
| INT | P3 |
| INT | P4 | |||||||||||
Set Port 1 |
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| P1 Flag | X |
| L | FFFF |
| X | FFFF |
| X | FFFF |
| X | |||||||
INT | |||||||||||||||||||||||
Reset Port 1 |
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| P1 Flag | FFFF |
| H | X |
| X | X |
| X | X |
| X | ||||||
INT | |||||||||||||||||||||||
Set Port 2 |
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| P2 Flag | FFFE |
| X | X |
| L | FFFE |
| X | FFFE |
| X | ||||||
INT | |||||||||||||||||||||||
Reset Port 2 |
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| P2 Flag | X |
| X | FFFE |
| H | X |
| X | X |
| X | ||||||
INT | |||||||||||||||||||||||
Set Port 3 |
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| P3 Flag | FFFD |
| X | FFFD |
| X | X |
| L | FFFD |
| X | ||||||
INT | |||||||||||||||||||||||
Reset Port 3 |
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| P3 Flag | X |
| X | X |
| X | FFFD |
| H | X |
| X | ||||||
INT | |||||||||||||||||||||||
Set Port 4 |
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| P4 Flag | FFFC |
| X | FFFC |
| X | FFFC |
| X | X |
| L | ||||||
INT | |||||||||||||||||||||||
Reset Port 4 |
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| P4 Flag | X |
| X | X |
| X | X |
| X | FFFC |
| H | ||||||
INT |
Note:
50.During Master Reset the control signals will be set to a deselected read state: CE0I = LBI = UBI = R/WI = MKLDI = MKRDI = CNTRDI = CNTRSTI = CNTLDI = CNTINCI = VIH; CE1I = VIL. The “I” suffix on all these signals denotes that these are the internal registered equivalent of the associated pin signals.
Document #: | Page 23 of 37 |
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