Cypress CY7C0430BV, CY7C0430CV AC Test Load

CY7C0430BV

CY7C0430CV

Document #: 38-06027 Rev. *B Page 9 of 37

AC Test Load

Note:

5. Test conditions: C = 10 pF.

VTH=1.5V

OUTPUT

(a) Normal Load

R = 50Ω

Z0 = 50Ω

[5]

3.0V

GND 90% 90%

10%

tRtF

10%

All Input Pulses

(b) Three-State Delay

VTH=1.5V

OUTPUT

5 pF

R = 50Ω

Z0 = 50Ω

(c) TAP Load

TDO

C= 10 pF

Z0=50Ω

GND

1.5V

50Ω

VTH=3.3V

OUTPUT

5 pF

R = 50Ω

Z0 = 50Ω

[+] Feedback

Contents

Main 10 Gb/s 3.3V QuadPort DSE Family Features QuadPort DSE Family Applications Functional Description CY7C0430BV CY7C0430CV Top Level Logic Block Diagram CY7C0430BV CY7C0430CV Port 1 Operation-Control Logic Block Diagram Pin Configuration 272-ball Grid Array (BGA) Top Vi ew Note: 4. Central Leads are for thermal dissipation only. They are connected to device VSS. 1234567891011121314151617181920 A B Selection Guide Pin Definitions CY7C0430BV CY7C0430CV Pin Definitions Maximum Ratings Operating Range Electrical Characteristics JTAG TAP Electrical Characteristics Capacitance AC Test Load (a) Normal Load (c) TAP Load (b) Three-State Delay All Input Pulses Switching Characteristics JTAG Timing and Switching Waveforms Switching Characteristics Switching Waveforms Read Cycle Bank Select Read Read-to-Write-to-Read (OE = VIL)[19, 20, 21, 22] Read-to-Write-to-Read (OE Controlled)[19, 20, 21, 22] Read with Address Counter Advance Write with Address Counter Advance Counter Reset Load and Read Address Counter Note 29 Note 30 Load and Read Mask Register Note 29 Note 30 Port 1 Write to Port 2 Read PORT-1 PORT-2 Counter Interrupt Mailbox Interrupt Timing Page Master Reset Interrupts Address Counter Control Operations Counter/ Address Register Counter-Mask Register IEEE 1149.1 Serial Boundary Scan (JTAG) and Memory Built-In-Self-Test (MBIST) Page Page Page CY7C0430BV CY7C0430CV JTAG/BIST TAP Controller Block Diagram Page Page Page Page Ordering Information Package Diagram Document History Page