Cypress CY7C0430BV, CY7C0430CV Read Cycle

CY7C0430BV

CY7C0430CV

Document #: 38-06027 Rev. *B Page 13 of 37

Read Cycle[12, 13, 14, 15, 16]

Notes:

12.OE is asynchronously controlled; all other inputs (excluding MRST) are synchronous to the rising clock edge.

13.CNTLD = VIL, MKLD = VIH, CNTINC = x, and MRST = CNTRST = VIH.

14.The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock.

15.Addresses do not have to be accessed sequentially. Note 13 indicates that address is constantly loaded on the rising edge of the CLK. Numbers are for reference

only.

16.CE is internal signal. CE = VIL if CE0 = VIL and CE1 = VIH.

Switching Waveforms (continued)

tCH2 tCL2

tCYC2

tSC tHC

tSW tHW

tSA tHA

AnAn+1

CLK

R/W

ADDRESS

DATAOUT

An+2 An+3

tSC tHC

tOHZ

tOE

tOLZ

tDC

tCD2

tCKLZ

QnQn+1 Qn+2

1 Latency

tSB tHB

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Contents

Main 10 Gb/s 3.3V QuadPort DSE Family Features QuadPort DSE Family Applications Functional Description CY7C0430BV CY7C0430CV Top Level Logic Block Diagram CY7C0430BV CY7C0430CV Port 1 Operation-Control Logic Block Diagram Pin Configuration 272-ball Grid Array (BGA) Top Vi ew Note: 4. Central Leads are for thermal dissipation only. They are connected to device VSS. 1234567891011121314151617181920 A B Selection Guide Pin Definitions CY7C0430BV CY7C0430CV Pin Definitions Maximum Ratings Operating Range Electrical Characteristics JTAG TAP Electrical Characteristics Capacitance AC Test Load (a) Normal Load (c) TAP Load (b) Three-State Delay All Input Pulses Switching Characteristics JTAG Timing and Switching Waveforms Switching Characteristics Switching Waveforms Read Cycle Bank Select Read Read-to-Write-to-Read (OE = VIL)[19, 20, 21, 22] Read-to-Write-to-Read (OE Controlled)[19, 20, 21, 22] Read with Address Counter Advance Write with Address Counter Advance Counter Reset Load and Read Address Counter Note 29 Note 30 Load and Read Mask Register Note 29 Note 30 Port 1 Write to Port 2 Read PORT-1 PORT-2 Counter Interrupt Mailbox Interrupt Timing Page Master Reset Interrupts Address Counter Control Operations Counter/ Address Register Counter-Mask Register IEEE 1149.1 Serial Boundary Scan (JTAG) and Memory Built-In-Self-Test (MBIST) Page Page Page CY7C0430BV CY7C0430CV JTAG/BIST TAP Controller Block Diagram Page Page Page Page Ordering Information Package Diagram Document History Page