S1F76640 Series

Note 1 : Precautions on Load Connection

When a load is connected between GND in the first stage (or potential below GND in the second stage other than that) and VREG in the second stage as shown in Figure 8.4, pay attention to the following. When a normal output is not available at the VREG pin at the starting time or when the POFF signal turns off VREG, current may flows from GND in the first stage (or potential below GND in the second stage other than that) to the VREG pin in the second stage through the load and a voltage higher than the absolute maximum rating below GND in the second stage may be generated at the VREG pin. As a result, the IC may not work normally. For series connection, connect the diode D1 between VDD and VREG in the second stage as shown in Figure 8.4, so that no potential below GND in the second stage is added to the VREG pin.

Note 2 : Figure 8.4 shows 3 times step-up in the first stage and 4 times step-up in the next stage, but 4 times step- up is possible both in the first stage and in the next stage unless the input voltage VDD’-GND’ exceeds the specification value (6.0V). This means that each IC in this series connection is requested t satisfy the specification values (VDD-GND ≤ 6, 0V, VO-GND ≤ 24V). (See Figure 8.5.)

 

 

First stage

Next stage

VO'

 

 

VREG'

 

 

 

 

 

VO

VDD'

 

 

 

 

Max. 6.0V

 

 

VDD

 

 

GND'

 

 

 

 

 

 

 

GND

Figure 8.5 Power Supply System in Series Connection

Note 3 : 2 times step-up in the first stage allows using the CAP- output in the first stage as the next stage clock, but 3 times step-up does not. Attach an external ROSC as the next stage clock for internal oscillation. Also, since the next stage external clock can operate according the CAP- output in the previous stage as shown in Table 4.1 only when the temperature gradient CT is -0.6%/˚C, use the internal oscillator in the same way when other temperature gradients are necessary.

Note 4 : In case of series connection, the voltage VDD-VREG(VREG’-V DD’ in Figure 8.5) of the IC, for which the stabilization circuit operates, has temperature gradient. This means that VREG changes at the following rate as temperature changes:

Δ⎥VREG⎥

S1F76640

Series

 

 

T

= CT (VREG’ (25˚C) – GND’)

S1F70000 Series Technical Manual

EPSON

2–59