Epson S1F70000 EPSON, S1F76540 Series, Clock Generator Circuit

S1F76540 Series

Table 2.4 AC characteristics

VDD = 0 V and VI = –5.0 V unless otherwise noted

Parameter	Symbol		Conditions		Min.	Typ.	Max.	Unit
		FC = VDD,		Ta = 25°C	3.0	4.0	6.0	kHz
Internal clock frequency 1	fCL1	POFF1 = VI
		POFF2	DD
			= V	Ta = –30°C	2.0	4.0	7.0	kHz
		Pin used: C1P		to +85°C
		FC = VI,		Ta = 25°C	12.0	16.0	24.0	kHz
Internal clock frequency 2	fCL2	POFF1 = VI
		POFF2	DD
			= V	Ta = –30°C	8.0	16.0	28.0	kHz
		Pin used: C1P		to +85°C

FUNCTIONAL DESCRIPTIONS

Clock Generator Circuit

As the S1F76540 has a built-in clock generator circuit, no more parts are required for voltage boost control. The clock frequency changes according to the FC pin voltage level as defined on Table 2.5. Low Output mode or High Output mode is selectable. This allows frequency selection according to the used capacitance and

Table 2.5 FC pin setup

load current as the boost output impedance changes depending on the clock frequency and external booster ca- pacitance. However, the High Output mode has the current consumption approximately four times larger than the Low Output mode.

					Characteristics
	FC pin	Mode	Clock frequency	Current	Output ripple	Output	Capacitance
				consumption		impedance
High (VDD)		Low Output	4.0 kHz (Typ.)	IOP (*1)	VRR (*2)	See Figure A1.	See Figure A1.
	Low (VI)	High Output	16.0 kHz (Typ.)	IOP × Approx. 4	VRI × Approx. 1/4	See Figure A1.	See Figure A1.
*1	See the DC characteristics table for current consumption.
*2	See Section Page 2-32 for the output ripple definition and calculation.

2–22 EPSON

S1F70000 Series Technical Manual