S1F76640 Series
PIN DESCRIPTIONS
Pin No. | Pin name | Description | ||
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1 |
| RV | Stabilization voltage regulation pin. | |
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| When the intermediate tap of the external volume |
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| connected between the VDD pin and the VREG pin is connected to the |
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| RV pin, VREG output voltage can be adjusted. |
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2 | VREG | Stabilized voltage output pin | ||
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3 |
| TC1 | Temperature gradient selection pin | |
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4 |
| TC2 | Temperature gradient selection pin | |
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5 |
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| VREG output ON/OFF control pin. |
| POFF | |||
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| When control signal from the system side is input to this pin, the power |
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| off (VREG output power off) control of S1F76640 becomes available. |
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6 |
| GND | Power supply pin (minus side, system GND) | |
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7 | OSC1 | Oscillation resistor connection pin. | ||
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| This pin becomes the clock input pin when an external clock operates. |
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8 | OSC2 | Oscillation resistor connection pin. | ||
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| This pin is released when an external clock operates. |
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9 |
| VDD | Power supply pin (plus side, system VCC) | |
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10 | CAP1– | Pump up capacitor minus side connection pin for 2 times | ||
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| Next stage clock at series connection time. |
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11 | CAP1+ | Pump up capacitor plus side connection pin for 2 times | ||
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12 | CAP2– | Pump up capacitor minus side connection pin for 3 times | ||
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| Output pin at 2 time |
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13 | CAP2+ | Pump up capacitor plus side connection pin for 3 times | ||
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14 | CAP3+ | Pump up capacitor plus side connection pin for 4 times | ||
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| Output pin at 3 times |
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15 |
| VO | Output pin at 3 times | |
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16 |
| VRI | Stabilization circuit input pin | |
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S1F76640 | Series |
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S1F70000 Series Technical Manual
EPSON |