S1F77200Y Series
The following figures show the input and output characteristics of the S1F77200Y series.
OUT | OUT |
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| VDET: Detection voltage | |||||||
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| VHYS |
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| VDET: Detection voltage |
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| VREL: Relief voltage | ||||||||||||
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| VREL: Relief voltage |
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0 |
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| VDD(V1) | 0 |
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| VDD(V1) |
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0 |
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| VDET VREL |
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| 0 |
| VDET | VREL | ||||||||||||||||||||||||
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Operating voltage | Operating voltage | Operating voltage |
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| Operating voltage | ||||||||||||||||||||||||||
| lower limit | upper limit |
| lower limit |
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| upper limit | ||||||||||||||||||||||
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| [S1F772*0Y1*0 Type] |
| S1F772*0Y2*0 Type | ||||||||||||||||||||||||||||||
Note: The above input/output characteristics assumes that the pull up resistor is connected to the output pin for the S1F77200Y series. For the S1F77220 series, it assumes that the pull down resistor is connected between the OUT and VDD pins.
If the input voltage that is applied between VDD and VSS terminals drops below the lower limit of voltage for IC operation, the output condition of the OUT terminal may become unsteady.
Ensure to prevent problems from occurring in circuit operation.
ABSOLUTE MAXIMUM RATINGS
Parameter | Symbol | Rating | Unit | |
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Supply voltage range | VDD – VSS | 15 | V | |
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| VDD + 0.3 to VSS – 0.3 |
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| (S1F77210) |
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Output voltage | VO | 15 to VSS – 0.3 | V | |
(S1F77200) | ||||
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| VDD + 0.3 to VDD – 15 |
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| (S1F77220) |
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Output current | IO | 50 | mA | |
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Allowable dissipation | PD | 200 | mW | |
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Operating temperature | Topr | °C | ||
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| (designed for lower voltage operation) |
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Storage temperature | Tstg | ˚C | ||
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Soldering temperature | Tsol | 260 · 10 | ˚C · s | |
and time | (at leads) | |||
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S1F77200Y | Series |
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S1F70000 Series Technical Manual
EPSON |