S1F77200Y Series
PIN DESCRIPTIONS
Pin No. | Pin name | Description |
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1 | OUT | Voltage detection output pin |
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2 | VDD | Input voltage pin (positive side) |
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3 | VSS | Input voltage pin (negative side) |
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PIN ASSIGNMENTS
1 2 3
FUNCTIONAL DESCRIPTIONS
The S1F77200Y series has the circuit configuration as shown in the figure below. For the detection, divided potential (VREG) across the resistors inserted across the power supply and the reference voltage (VREF) generated on the IC are entered to the voltage comparator. Since the voltage comparator is designed to detect a target voltage even when potential difference between VREG and Vref minute, hysteresis is added so that the comparator may not fail due to noise on the power supply and such. In the example shown in the figure below,
detection voltage (VDET) for the input voltage drop and relief voltage (VREL) for the increased input voltage are set based the following formula.
Detection voltage: VDET = | R1+R2+R3 | • VREF | |
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| R2+R3 |
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Relief voltage: | VREL = | R1+R2+R3 | • VREF |
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| R3 |
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VDD
(2pin)
R1
| (VREG) |
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T | + |
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R2 | — | OUT |
(1pin) | ||
T | VREF |
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| |
R3 |
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VSS
(3pin)
EPSON |
S1F70000 Series Technical Manual