S1F76600 Series
TYPICAL APPLICATIONS
Parallel ConnectionConnecting two or more chips in parallel reduces the output impedance by 1/n, where n is the number of devices used.
VDD = 0 V
5 V
VI =
1 | 8 | + |
| C2 | 1 | 8 |
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1MΩ | 2 | 7 |
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| 1MΩ | 2 | 7 |
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| 3 | 6 |
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| 4 | 5 | + |
| 10∝F |
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VO =
Connecting two or more chips in series obtains a higher output voltage than can be obtained using a parallel
connection, however, this also raises the output imped- ance.
| VDD = 0 V |
VI = | 5 V |
VDD' = VI = |
1 | 8 | + |
| C2 | 1 | 8 | + | C2 | ||||
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| 10∝F |
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1MΩ | 2 | 7 |
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| 3 | 6 |
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| C1 | 3 | 6 |
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| 4 | 5 | + |
| 10∝F | 4 | 5 | + | 10∝F | |||
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| VO' = |
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| VO = |
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Potential levels
VDD (0 V)
VI 
VDD'
VO |
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Primary stage |
| Secondary stage | ||
EPSON |
S1F70000 Series Technical Manual