
S1F76540 Series
Figure 2.8 gives a wiring example of
negative direction, and outputs the regulated voltage at VREG pin.
CO
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VREG | CREG | 1 | VO | C2P 16 | + | |
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R1 | + | 2 | VRI | C2N 15 | C2 | |
R2 | 3 | VREG | C3N 14 |
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| 4 | RV | C1N | 13 | C1 |
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VDD |
| 5 | VDD | C1P | 12 | + |
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| 6 | FC | VI | 11 |
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| + | 7 | TC1 | POFF1 10 |
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CI |
| 8 | TC2 | POFF2 | 9 |
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VI
Figure 2.8 Wiring example of
◊Setup conditions of Figure 2.8
• Internal clock | : ON (Low Output mode) |
• Booster circuit : ON | |
• Regulator | : ON (if CT = |
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•Set the POFF1 pin to logical low (VI) to turn off all circuits.
◊Regulator
•For the regulator setup and notes, see the “voltage regulator circuit” section.
◊Application in other setup conditions
1 When used in the High Output mode
• Connect the FC pin to the VI pin.
2When changing the temperature coefficient (CT)
• Change the TC1 and TC2 pin setup by following the definition of Table 2.7.
EPSON |
S1F70000 Series Technical Manual