S1F76640 Series
Configuration Example of Voltage Stabilized Output (VREG) Electronic Volume Circuit
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| Voltage stabilized output (VREG) |
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| 16 | VRI | RV | 1 |
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| 15 | VO | VREG | 2 |
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– |
| 14 | CAP3+ | TC1 | 3 | VSS or VO |
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+ + | 13 | CAP2+ | TC2 | 4 | VSS or VO |
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– | – | 12 | CAP2– | POFF | 5 |
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| + | 11 | CAP1+ | VSS | 6 | 13 | IN0 |
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| 7 | 14 | IN1 | COM | 3 |
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| 10 | CAP1– | OSC1 | 15 | IN2 |
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| 9 | VDD | OSC2 | 8 | 12 | IN3 |
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| 1 | IN4 |
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| 5 |
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| IN5 |
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| XPOF | 2 |
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| IN6 |
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| (VDD/VSS) | 4 | A | CTRL0 | |||
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| B | 10 | CTRL1 | |
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| C | 9 | CTRL2 |
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| INH | 6 |
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| 16 | VCC |
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| VEE VSS |
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| 7 | 8 |
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Negative voltage input
Positive voltage input
Figure 8.9
EPSON |
S1F70000 Series Technical Manual