S1F76300 Series

Reference voltage generator and output voltage regulator

The reference voltage generator regulates VI1 to generate a votlage for the voltage regulator and voltage detection circuits.

The voltage regulator regulates the boosted output votlage. This is determined by the level at point A between the two resistors connecting VO and GND. These series use an on-chip resistor to set the output at a specified voltage.

Reference

Output

voltage

voltage regulator

generator

 

VI1

VSW

CR

oscillator

VO

A

+

–

GND

Note

In step-up voltage operation, the ripple voltage created by the switching operation is large relative to the output voltage described above. This ripple voltage is affected by external components and load conditions. The user is advised to check this voltage carefully.

Voltage detection

The S1F76310, S1F76380 series are equipped with a built-in voltage detection function. The detection volt- age, VDET, is fixed internally at 1.05 ± 0.05V.

Power-on clear function

The S1F76310 series and S1F76380 series are equipped with a built-in power-on clear function. As shown in the following figure, R1 and C1 are connected to PWCR, and R2 is connected to RST to operate the func- tion. If VI1 drops below VDET, Tr1 and Tr2 conduct and PWCR and RST are grounded. If VI1 recovers and rises higher than VREL, Tr1 turns OFF. The detection voltage hysteresis is 5% (Typ.) and VREL is VDET × 1.05 (Typ.).

S1F76310M

VO

 

Voltage

 

detector

R2

 

RST

Tr2 VO

VO

VI1

 

 

R1

 

PWCR

–

 

Tr1

C1

+

VO returns to its normal value when the voltage of PWCR increases and Tr2 turns OFF, so that RST returns to VO after a delay specified by the time coefficient of R1 and C1. Thus, after normal output has been obtained, a reset pulse of adjustable width can be obtained which can reset a system connected to RST.

The output from RST is an N-channel, open-drain. When VI1 exceeds VDET, the drain is opened and, when VI1 drops below VDET again, the output transistor conducts and the output is grounded. The characteristic response is shown in the following figure.

VREL

VI1

VDET

VO

PWCR

VGND

VO

RST

VGND

Disabling power-on clear

Always connect PWCR to either VO or GND. If voltage detection only is required, remove the resistor between PWCR and VO and monitor the level at RST. If neither function is required, connect PWCR to GND.

Leaving PWCR unconnected results in an undefined inverter gate voltage in the VO circuit, causing transient currents to flow between VO and GND.

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EPSON

S1F70000 Series Technical Manual