
S1F76540 Series
The S1F76540 has the
in parallel connection and other application circuits. To use the
Table 2.7 Available combination of
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| POFF1 |
| POFF2 |
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| (High = VDD) | (High = VDD) | Oscillator | Booster | Regulator | Applications | ||||
Mode | (Low = VI) | (Low = VI) |
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PS1 |
| High |
| Low | ON | ON | ON | All circuits are turned on. | ||
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PS2 |
| Low |
| Low | OFF | OFF (*1) | OFF (*2) | All circuits are turned off. | ||
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PS3 |
| High |
| High | OFF | ON | ON | Slave unit side of parallel connection | ||
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PS4 |
| Low |
| High | ON | ON | OFF | Master unit side of parallel | ||
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*1 When the booster circuit is off, approximately VI + 0.6 V voltage appears at VO pin. *2 When the regulator is off, the VREG pin becomes
Application notes on
•When using external system signals for
VI | VI |
| POFF1 |
POFF1 | |
| POFF2 |
POFF2 |
Figure 2.6 Start timing of
EPSON |
S1F70000 Series Technical Manual