Epson S1F70000 EPSON, S1F76540 Series, Parallel Connection (for Increased Boosting)

S1F76540 Series

					VRP
	IO
VRP =			+ IO • RCOUT	• • • • Equation (4)
	2 • fCL
		• CO

where,

IO : Load current (A)

fCL : Clock frequency (Hz)

RCOUT : Serial equivalent resistance (Ω) of output capacitor CO

Figure 2.10 Ripple waveforms

◊Application in other setup conditions

1 When used in the High Output mode Connect the FC pin to the VI pin.

Parallel Connection (for Increased Boosting)

The parallel connection is useful for reduction of booster output impedance or reduction of ripple volt- age. In the parallel connection of “n” lines, the booster output impedance can be reduced to approximately “1/ n". Only the smoothing capacitor (CO) for booster output can be used commonly in the parallel connection. When using the regulator, use only one of “n”

S1F76540 chips which are in parallel connection. (If multiple regulators are operated in parallel mode, the reactive current consumption occurs.) Figure 2.11 gives a wiring example of 4-time booster and regulator where two S1F76540s are parallelly connected.

								VREG
+
CO	1	VO	C2P 16		+		CREG	1	VO	C2P 16	+
	2	VRI	C2N 15		C2	+	R2	2	VRI	C2N 15	C2
	3	VREG	C3N 14			R1		3	VREG	C3N 14
						C3					C3
					C1
	4	RV	C1N	13		+		4	RV	C1N 13	C1
											+
VDD	5 VDD		C1P 12		+			5	VDD	C1P 12	+
	6	FC	VI	11				6	FC	VI 11
+	7 TC1		POFF1 10					7	TC1	POFF1 10
CI	8	TC2	POFF2	9				8	TC2	POFF2 9
VI

Figure 2.11 Parallel connection example

2–32 EPSON

S1F70000 Series Technical Manual