S1F76640 Series

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CAP3+=4VDD=20V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note

 

3

 

CAP1+=2VDD=10V

 

 

 

CAP2+=3VDD=15V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note

 

2

 

 

 

 

 

 

 

Note

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDD=5V

 

 

 

 

 

 

 

VDD=5V

 

 

 

 

 

 

 

 

VDD=5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND=0V

 

 

 

 

 

 

 

GND=0V

 

 

 

 

 

 

 

 

GND=0V

 

 

 

 

 

 

 

 

Figure 5-3

Figure 5-4

 

Figure 5-5

Example of 2 times step-up

Example of 3 times step-up

Example of 4 times step-up

potential relations

potential relations

potential relations

Note 1 : At the 3 times step-up time, 2 times step-up output (–10V) cannot be taken out from the CAP2– pin.

Note 2 : At the 4 times step-up time, 2 times step-up output (–10V) cannot be taken out from the CAP2– pin.

Note 3 : At the 4 times step-up time, 3 times step-up output (–15V) cannot be taken out from the CAP3– pin.

Reference Voltage Generator, Voltage Stabilization Circuit

The reference voltage generator generates reference voltage necessary for operation of the voltage stabilization circuit and adds temperature gradient to reference voltage. Three temperature gradients are available, and signal from the temperature gradient selection circuit select one of them.

The voltage stabilization circuit stabilizes the step-up output voltage VO and outputs optional voltages. When an external resistor RRV is connected as shown in Figure 5-5 and the potential of the intermediate tap is changed, VREG output voltage can be set to optional voltages between the reference voltage VRV and VO.

VSS

 

POFF

Control signal

 

RV

R1

RRV=100kΩ to 1MΩ

VREG

VREG = RRV · VRV

 

 

R1

Figure 5-6 Voltage Stabilization Circuit

The voltage stabilization circuit has power off function and can control ON/OFF of VREG output according to signals from the system side (microprocessor, etc.) When POFF is high (VDD), VREG output is turned on, and when POFF is Low (GND), it is turned off. When the control is not necessary, POFF is fixed to High (VDD).

2–44

EPSON

S1F70000 Series Technical Manual