Epson S1F70000 EPSON, S1F76540 Series, Larger Time Boosting Using Diodes

S1F76540 Series

◊Setup conditions of Figure 2.11

	First stage		Second stage
• Internal clock	: ON (Low Output mode)	• Internal clock	: OFF
• Booster circuit : ON		• Booster circuit : ON
• Regulator	: OFF	• Regulator	: ON (if CT = –0.04%/°C)

◊Power-off procedure

•In Figure 2.11, when the POFF2 pin of the first-stage S1F76540 is set to low (VI), voltage boosting is stopped at the first and second stages. However, the regulator at the second stage does not stop. Therefore, the voltage that is approximately VI appears at VREG pin during VREG > VI setup.

•To set the VREG pin to high-impedance state, set both POFF1 and POFF2 pins to low at the first and second stages.

◊Application in other setup conditions

1 When used in the High Output mode

•Connect the FC pin of the first-stage S1F76540 to the VI pin. 2 When changing the temperature coefficient (CT)

•Change the TC1 and TC2 pin setup by following the definition of Table 2.7.

Larger Time Boosting Using Diodes

The S1F76540 can be configured to have the five-time

Figure 2.12 gives a wiring example of 6-time booster

or larger voltage boosting and regulation by adding ex-

and regulator that use two diodes. The wiring between

ternal diodes. As the booster output impedance in-

VO and VRI must be minimal. Figure 2.13 provides the

creases due to the diode forward voltage drop (VF), the

potential relationship.

diodes having a smaller VF are recommended to use.

VO'

VREG

C2P 16

CREG

VRI

C2N

VREG

C3N

C1N

VDD

C1P

6 FC

7 TC1

POFF1

8 TC2

POFF2

Figure 2.12 Wiring example for 6-time boosting using diodes

S1F76540	Series

S1F70000 Series Technical Manual

EPSON

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