Epson S1F70000 EPSON, S1F76610 Series, Parallel Connection, Voltage Tripler with Regulator, Converting a Voltage Tripler to a Voltage Doubler

S1F76610 Series

TYPICAL APPLICATIONS

Voltage Tripler with Regulator

The following figure shows the circuit required to triple the input voltage, regulate the result and add a temperature gradient of –0.4%/°C. Note that the high input impedance of RV requires appropriate noise countermea- sures.

VDD = 0 V

	C1	+	1	14
	10 ∝F					R1	RRV
			2	13	ROSC
							100 kΩ
	5 V C2	+	3	12	1 MΩ	R2	to
	10 ∝F		4	11			1 MΩ	+C4
								10 ∝F
			5	10
			6	9			VREG = –8 V
			7	8	VO = –15 V			RRV
VI = –5 V			+ C3					= R1	VRV

10∝F

Converting a Voltage Tripler to a Voltage Doubler

To convert this curcuit to a voltage doubler, remove capacitor C2 and short circuit CAP2– to VO.

VDD = 0 V
	C1 +	1	14
	10∝F	2	13	ROSC
				1 MΩ
	5V C2 +	3	12
	10∝F
		4	11
		5	10
		6	9
				VO = –15 V
VI = –5 V		7	8
		+	C3

10∝F

Parallel Connection

Connecting two or more chips in parallel reduces the output impedance by 1/n, where n is the number of devices used.

Only the single output smoothing capacitor, C3, is re-

quired when any number of devices are connected in parallel. Also, the voltage regulator in one chip is sufficient to regulate the combined output.

VDD = 0 V
	C1	+	1	14			Χ1		+	1	14
	10 ∝Φ					10 ∝Φ							Ρ Ρς
			2	13	Ρ ΟΣΧ					2	13	Ρ ΟΣΧ
													100 κ Ω
					1 ΜΩ							1 ΜΩ
													το
	Χ2	+	3	12			Χ2		+	3	12
													1 ΜΩ
	10 ∝Φ					10 ∝Φ
			4	11						4	11		+	Χ4
	5 V													10 ∝Φ
			5	10						5	10
			6	9						6	9
													VREG = –10 V
VI = –5 V			7	8						7	8	VO = –15 V
								+Χ3
							10 ∝Φ

2–12 EPSON

S1F70000 Series Technical Manual