S1F79100Y Series

Differential amplifier

The built-in differential amplifier generates a potential at point X that adjusts the gate bias of the output transistor if there is any difference betweeen VREF and VREG.

 

VSS

 

 

VREF

P1

P2

VREG

X

To output

transistor

 

N1 N2

VI

Output transistor

The output side of the p-channel MOS transistors in the output transistor circuit is connected to the voltage divider resistors in the feedback loop.

VSS

R1

VREF

VREG

R2

VO

+

–

V1

TYPICAL APPLICATIONS

Current Booster

At the cost of a small increase in current consumption, the voltage is regulated while maintaining high current output.

VSS

GND

VIVO

S1F79100Y

VI VO

External Voltage Converter

The following circuit raises the output voltage of a S1F79100Y series IC.

VSS

R1

IOPR

The following equation shows the relationship between the old and new voltages.

R1 + R2

VO = — — — — — V R

R2

Note that the application must supply a bias current, IB, high enough to offset the increase in voltage across R1 due to IOPR.

An alternative circuit for raising the output voltage is shown in the following figure.

VSS

 

ISS

CO

R1

 

CI

 

GND

 

 

VI

VI S1F79100Y VO

 

VO

This configuration, however, introduces two design problems.

GND

IB

Vr R2

1. It reduces the output voltage by VF, the forward volt-

age drop across the diode.

2. It is sensitive to fluctuations in VF due to differences

VI

S1F79100Y

VO

VIVO

in diodes, operating temperatures and ISS.

3–36

EPSON

S1F70000 Series Technical Manual