6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm
218 IBM eServer zSeries 990 Technical Guide
z990 introduces a new microprocessor architecture exploiting the CMOS9S-SOI technology
while improving uniprocessor performance. A significant capacity and throughput increase
has been achieved with the introduction of:
򐂰Up to 32 Processor Units as CPs, IFLs, ICFs, or zAAPs, for operating systems
򐂰Up to 8 Processor Units as standard System Assist Processors (SAPs), for I/O processing
򐂰Up to 30 logical partitions
򐂰Up to 256 GB of memory
򐂰Up to 96 GB/sec of bandwidth for data communication via up to 48 Self-Timed
Interconnect (STI) host buses
򐂰A new Channel Subsystem (CSS): four Logical Channel Subsystems (LCSSs) can exist
for horizontal growth, supporting up to 256 CHPIDs per CSS for a total of 1024 CHPIDs
per system
򐂰Increased channel maximums for ESCON, FICON Express, and OSA-Express
򐂰Three cryptographic features:
– New CP Assist for Cryptographic Function (CPACF)
– New PCIX Cryptographic Coprocessor (PCIXCC)
– PCI Cryptographic Accelerator (PCICA)
򐂰Integrated Cluster Bus-4 (ICB-4), capable of up to 2 GB/sec
Some of the most important performance related topics are: the balanced system design, the
superscalar processors, and the integrated hardware and system assists.
8.7.1 Balanced system design
One of the most important design objectives of a zSeries server is to build a balanced
system. This means a system with no specific constraints, where individual parts, such as
processor speed, memory bandwidth, and I/O bandwidth, are designed for the server’s best
performance and throughput.
The balanced system design is also based on the fact that no single component just by itself,
like processor frequency (expressed in GHz), can improve the system’s overall performance
for a wide range of workloads and applications.
The z990 servers have performance improvements on all workload environments, from
traditional to e-business on demand. Comparing to the z900 turbo servers, the z990 has
improved all major components:
򐂰Maximum number of assigned processors, from 16 to 32
򐂰Processor cycle time, from 1.09 ns to 0.83 ns
򐂰L2 caches, from 32 MB per 20 PUs to 32 MB per 12 PUs
򐂰Maximum memory size, from 64 GB to 256 GB
򐂰STI bandwidth, from 1 GB/sec to 2 GB/sec per STI
򐂰Maximum number of STIs, from 24 to 48 STIs
򐂰Maximum I/O bandwidth, from 24 GB/sec to 96 GB/sec
򐂰Maximum number of channels, from 256 to 1024

Additional performance improvements for e-business

z990 has also further performance improvements for e-business application environments: