IBM 990 manual Compression Unit on a chip, CP Assist for Cryptographic Function

Draft Document for Review April 7, 2004 6:15 pm 6947ch02.fm

	From L2 Cache
From E-Unit		From E-Unit
I-Unit	B-Unit	I-Unit
	L1
	Cache
E-Unit	To L2 Cache	E-Unit
	R-Unit
Floating p	COMPARE	Floating p
Fixed p	Error	Fixed p
	Detection
To B-Unit		To B-Unit

Processing Unit (PU)

Dual processor I-Unit

E-Unit

Floating Point function

Simple yet complete error detection mechanism

Data flow - parity checked Address paths - parity checked L1 Cache - parity checked Processor logic (I - E - F) -

Duplicated, then compared output. Error detection for mis-compare

Figure 2-13 Dual (asymmetric) processor design

Each PU has a dual processor and each processor has its own Instruction Unit (I-Unit) and Execution Unit (E-Unit), which includes the floating point function. The instructions are executed asymmetrically (not exactly in parallel) on each processor and compared after processing.

This design simplifies error detection during instruction execution, saving additional circuits and extra logic required to do this checking. The z990 servers also contain error-checking circuits for data flow parity checking, address path parity checking, and L1 cache parity checking.

Compression Unit on a chip

Each z990 PU has a Compression Unit on the chip, providing excellent hardware compression performance. The Compression Unit is integrated with the CP Assist for Cryptographic Function, benefiting from combining the use of buffers and interfaces.

CP Assist for Cryptographic Function

Each z990 PU has a CP Assist for Cryptographic Function on the chip. The assist provides high performance hardware encryption and decryption support for clear key operations. To that end, five new instructions are introduced with the cryptographic assist function.

The CP Assist for Cryptographic Function offers a set of symmetric cryptographic functions that enhance the encryption and decryption performance of clear key operations for SSL, VPN, and data storing applications that do not require FIPS 140-2 level 4 security. The cryptographic architecture includes DES, T-DES data encryption and decryption, MAC message authorization, and SHA-1 hashing.

The CP Assist for Cryptographic Function complements public key (RSA) functions and the secure cryptographic operations provided by the PCIXCC cryptographic coprocessor card.

See Chapter 5, “Cryptography” on page 119, for more information about the cryptographic features on the z.990.

Chapter 2. System structure and design 43