6947ch02.fm

Draft Document for Review April 7, 2004 6:15 pm

under way to update the C++ compiler and Java Virtual Machine for z/OS to better exploit the z990 microprocessor superscalar implementation. The intent is improve the performance advantage for e-business workloads such as WebSphere and Java applications.

By the time the Java Virtual Machine (JVM) and compilers are available, more improvement in the throughput of the superscalar processor is expected. In order to create instruction sequences that are least affected by interlock situations, instruction grouping rules are enforced to create instruction streams that benefit most from the superscalar processor. It is expected that e-business workloads will primarily benefit from this design since they tend to use more computational instructions.

A WebSphere Application Server workload environment that runs a mix of Java and DB2® code will greatly benefit from the superscalar processor design of the z990. Measurements already show a larger than 20% performance improvement for these types of workloads, on top of the improvements attributed to the cycle time decrease from 1.09 ns on a z900 Turbo model to 0.83 ns on a z990.

The superscalar design of the z990 microprocessor means that some instructions are processed immediately and that processing steps of other instructions may occur out of the normal sequential order, called “pipelining”. The superscalar design of the z990 offers:

￿Decoding of two instructions per cycle

￿Execution of three instructions per cycle (given that the oldest instruction is a branch)

￿In-order execution

￿Out-of-order operand fetching

Other features of the microprocessor, aimed at improving the performance of the emerging e-business application environment, are:

￿Floating point performance for IEEE Binary Floating Point arithmetic is improved to assist further exploitation of Java application environments.

￿A secondary cache for Dynamic Address Translation, called the Secondary level Translation Look aside Buffer (TLB), is provided for both L2 instruction and data caches, increasing the number of buffer entries by a factor of eight.

￿The CP Assist for Cryptographic Function (CPACF) accelerates the encryption and decryption of SSL transactions and VPN encrypted data transfers. The assist function uses five new instructions for symmetrical clear key cryptographic encryption and encryption operations.

Asymmetric mirroring for error detection

Each PU in the z990 servers uses mirrored instruction execution as a simple error detection mechanism. The mirroring is dependent on a dual instruction processor design with dual I-units, and E-units and floating point function. It is asymmetric because the mirrored execution is delayed from the actual operation. The benefit of the asymmetric design is that the mirrored units do not have to be closely located to the units where the actual operation takes place, thus allowing for optimization for performance.(see Figure 2-13).

42IBM eServer zSeries 990 Technical Guide

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IBM 990 manual Asymmetric mirroring for error detection

990 specifications

The IBM 990 series, often referred to in the context of IBM's pioneering efforts in the realm of mainframe computing, represents a unique chapter in the history of information technology. Introduced in the late 1960s, the IBM 990 series was designed as a powerful tool for enterprise-level data processing and scientific calculations, showcasing the company's commitment to advancing computing capabilities.

One of the main features of the IBM 990 was its architecture, which was built to support a wide range of applications, from business processing to complex scientific computations. The system employed a 32-bit word length, which was advanced for its time, allowing for more flexible and efficient data handling. CPUs in the IBM 990 series supported multiple instructions per cycle, which contributed significantly to the overall efficiency and processing power of the machines.

The technology behind the IBM 990 was also notable for its use of solid-state technology. This provided a shift away from vacuum tube systems that were prevalent in earlier computing systems, enhancing the reliability and longevity of the hardware. The IBM 990 series utilized core memory, which was faster and more reliable than the magnetic drum memory systems that had been standard up to that point.

Another defining characteristic of the IBM 990 was its extensibility. Organizations could configure the machine to suit their specific needs by adding memory, storage, and peripheral devices as required. This modular approach facilitated the growth of systems alongside the technological and operational demands of the business environments they served.

In terms of software, the IBM 990 series was compatible with a variety of operating systems and programming environments, including FORTRAN and COBOL, enabling users to access a broader array of applications. This versatility was a significant advantage, making the IBM 990 an appealing choice for educational institutions, research facilities, and enterprises alike.

Moreover, the IBM 990 was engineered to support multiprocessing, which allowed multiple processes to run simultaneously, further increasing its effectiveness in tackling complex computing tasks.

In summary, the IBM 990 series represents a significant advancement in computing technology during the late 20th century. With a robust architecture, versatile configuration options, and a focus on solid-state technology, the IBM 990 facilitated substantial improvements in data processing capabilities, making it a cornerstone for many businesses and academic institutions of its time. Its impact can still be seen today in the continued evolution of mainframe computing.